Valery Salauyou

13 papers C 1Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Complexity of Area and Performance Estimates of Finite State Machines. CISIM Valery Salauyou
2023	—	`conf`	Fault Detection of Moore Finite State Machines by Structural Models. CISIM Valery Salauyou
2022	—	`conf`	Embedded Processor Design in FPGA by ASMD-FSMD and FSM-Single Techniques. CISIM Valery Salauyou
2021	—	`conf`	Digital Device Design by ASMD-FSMD Technique. CISIM Valery Salauyou, Adam Klimowicz
2020	—	`conf`	The Synthesis Method of High-Speed Finite State Machines in FPGA. CISIM Valery Salauyou, Damian Borecki, Tomasz Grzes
2019	—	`conf`	Coding Techniques in Verilog for Finite State Machine Designs in FPGA. CISIM Valery Salauyou, Lukasz Zabrocki
2018	—	`conf`	High-Speed Finite State Machine Design by State Splitting. DepCoS-RELCOMEX Damian Borecki, Valery Salauyou, Tomasz Grzes
2018	—	`conf`	Synthesis of High-Speed ASM Controllers with Moore Outputs by Introducing Additional States. CISIM Valery Salauyou, Irena Bulatowa
2017	—	`conf`	State Assignment of Finite-State Machines by Using the Values of Input Variables. CISIM Valery Salauyou, Michal Ostapczuk
2016	—	`conf`	Synthesis of High-Speed Finite State Machines in FPGAs by State Splitting. CISIM Valery Salauyou
2015	—	`conf`	Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC. CISIM Valery Salauyou, Marek Gruszewski
2012	C	`conf`	The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States. DSD Adam Klimowicz, Valery Salauyou
2007	—	`conf`	FSM State Assignment Methods for Low-Power Design. CISIM Valery Salauyou, Tomasz Grzes