Valerio Tenace

31 papers A* 1A 5C 5Journal 12Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Automated Generation of Microfluidic Netlists using Large Language Models. CoRR Jasper Davidson, Skylar Stockham, Allen Boston, Ashton Snelgrove, Valerio Tenace, Pierre-Emmanuel Gaillardon
2025	J	`jnl`	Adaptive Multi-Agent Reasoning via Automated Workflow Generation. CoRR Humza Sami, Mubashir ul Islam, Pierre-Emmanuel Gaillardon, Valerio Tenace
2025	C	`conf`	Automated Generation of Microfluidic Netlists using Large Language Models. VLSI-SoC Jasper Davidson, Skylar Stockham, Allen Boston, Ashton Snelgrove, Valerio Tenace, Pierre-Emmanuel Gaillardon
2025	A	`conf`	EDA-Aware RTL Generation with Large Language Models. DATE Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2025	J	`jnl`	Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation. CoRR Humza Sami, Mubashir ul Islam, Samy Charas, Asav Gandhi, Pierre-Emmanuel Gaillardon, Valerio Tenace
2024	J	`jnl`	AIvril: AI-Driven RTL Generation With Verification In-The-Loop. CoRR Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2024	J	`jnl`	EDA-Aware RTL Generation with Large Language Models. CoRR Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	—	`conf`	NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	J	`jnl`	Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2019	A	`conf`	Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE Luca Mocerino, Valerio Tenace, Andrea Calimera
2019	J	`jnl`	Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet Matteo Grimaldi, Valerio Tenace, Andrea Calimera
2019	A	`conf`	SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera
2018	—	`conf`	A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera
2018	C	`conf`	Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC Valerio Tenace, Andrea Calimera
2018	C	`conf`	Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera
2018	J	`jnl`	Quasi-exact logic functions through classification trees. Integr. Valerio Tenace, Andrea Calimera
2017	—	`conf`	Activation-Kernel Extraction through Machine Learning. NGCAS Valerio Tenace, Andrea Calimera
2016	—	`—`	CAD Tools for Graphene-Based Electronic Circuits. Valerio Tenace
2016	C	`conf`	Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	—	`conf`	Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	—	`conf`	Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	C	`conf`	Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2016	J	`jnl`	Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	—	`conf`	Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2015	A*	`conf`	One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	J	`jnl`	Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	A	`conf`	Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	J	`jnl`	Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2012	—	`conf`	NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino