Valeria Bertacco

172 papers A* 35A 46B 2C 11Misc 5Journal 31Unranked 39

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective. IEEE Des. Test Aida Todri-Sanial, Theocharis Theocharides, Valeria Bertacco, Alberto Bosio
2025	A	`conf`	GLEAM: Graph-Based Learning Through Efficient Aggregation in Memory. DATE Andrew McCrabb, Ivris Raymond, Valeria Bertacco
2025	J	`jnl`	GreenScale: Carbon Optimization for Edge Computing. IEEE Internet Things J. Yonglak Son, Udit Gupta, Andrew McCrabb, Young-geun Kim, Valeria Bertacco, David Brooks, Carole-Jean Wu
2025	A	`conf`	SPIRE: Inferring Hardware Bottlenecks from Performance Counter Data. DATE Nicholas Wendt, Mahesh Ketkar, Valeria Bertacco
2024	J	`jnl`	DATE 2024: Consolidating the New Conference Format. IEEE Des. Test Andy D. Pimentel, Valeria Bertacco, Aida Todri-Sanial, Theocharis Theocharides
2024	A*	`conf`	Duet: A Collaborative User Driven Recommendation System for Edge Devices. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2024	—	`conf`	Evergreen: Comprehensive Carbon Model for Performance-Emission Tradeoffs. IISWC Tersiteab Adem, Andrew McCrabb, Vidushi Goyal, Valeria Bertacco
2023	A*	`conf`	ACRE: Accelerating Random Forests for Explainability. MICRO Andrew McCrabb, Aymen Ahmed, Valeria Bertacco
2023	J	`jnl`	GreenScale: Carbon-Aware Systems for Edge Computing. CoRR Young Geun Kim, Udit Gupta, Andrew McCrabb, Yonglak Son, Valeria Bertacco, David Brooks, Carole-Jean Wu
2023	J	`jnl`	Postpandemic Conferences: The DATE 2023 Experience. IEEE Des. Test Ian O'Connor, Robert Wille, Andy D. Pimentel, Valeria Bertacco
2022	J	`jnl`	Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic. IEEE Trans. Computers Doowon Lee, Valeria Bertacco
2022	—	`conf`	DyGraph: a dynamic graph generator and benchmark suite. GRADES-NDA@SIGMOD Andrew McCrabb, Hellina Nigatu, Absalat Getachew, Valeria Bertacco
2022	J	`jnl`	Hardware-friendly User-specific Machine Learning for Edge Devices. ACM Trans. Embed. Comput. Syst. Vidushi Goyal, Reetuparna Das, Valeria Bertacco
2022	A*	`conf`	PriMax: maximizing DSL application performance with selective primitive acceleration. DAC Nicholas Wendt, Todd M. Austin, Valeria Bertacco
2021	B	`conf`	A Defense-Inspired Benchmark Suite. ISPASS Pete Ehrett, Nathan Block, Bing Schaefer, Adrian Berding, John Paul Koenig, Pranav Srinivasan, Valeria Bertacco, Todd M. Austin
2021	—	`conf`	ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems. ISQED Hiwot Tadese Kassa, Tarunesh Verma, Todd M. Austin, Valeria Bertacco
2021	C	`conf`	Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets. ICCD Pete Ehrett, Todd M. Austin, Valeria Bertacco
2021	Misc	`conf`	Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2021	—	`conf`	Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HOST Austin Harris, Tarunesh Verma, Shijia Wei, Lauren Biernacki, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd M. Austin
2021	—	`conf`	Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HCS Todd M. Austin, Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari
2021	A*	`conf`	MyML: User-Driven Machine Learning. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2021	J	`jnl`	Optimizing Vertex Pressure Dynamic Graph Partitioning in Many-Core Systems. IEEE Trans. Computers Andrew McCrabb, Valeria Bertacco
2020	A*	`conf`	Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics. DAC Abraham Addisie, Valeria Bertacco
2020	J	`jnl`	Collaborative Accelerators for Streamlining MapReduce on Scale-up Machines With Incremental Data Aggregation. IEEE Trans. Computers Abraham Addisie, Valeria Bertacco
2020	A	`conf`	GraphVine: Exploiting Multicast for Scalable Graph Analytics. DATE Leul Belayneh, Valeria Bertacco
2020	A	`conf`	Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. IPDPS Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das
2020	A*	`conf`	Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2020	—	`conf`	Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces. HOST Lauren Biernacki, Mark Gallagher, Valeria Bertacco, Todd M. Austin
2019	—	`conf`	Collaborative accelerators for in-memory MapReduce on scale-up machines. ASP-DAC Abraham Addisie, Valeria Bertacco
2019	A*	`conf`	DREDGE: Dynamic Repartitioning during Dynamic Graph Execution. DAC Andrew McCrabb, Eric Winsor, Valeria Bertacco
2019	A	`conf`	MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph Analytics. ISLPED Leul Belayneh, Abraham Addisie, Valeria Bertacco
2019	A*	`conf`	Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin
2019	A	`conf`	SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design. DATE Pete Ehrett, Todd M. Austin, Valeria Bertacco
2018	—	`conf`	Heterogeneous Memory Subsystem for Natural Graph Analytics. IISWC Abraham Addisie, Hiwot Kassa, Opeoluwa Matthews, Valeria Bertacco
2018	C	`conf`	Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems. ICCD Doowon Lee, Opeoluwa Matthews, Valeria Bertacco
2018	A	`conf`	SWAN: mitigating hardware trojans with design ambiguity. ICCAD Timothy Linscott, Pete Ehrett, Valeria Bertacco, Todd M. Austin
2018	A	`conf`	Symbolic assertion mining for security validation. DATE Alessandro Danese, Valeria Bertacco, Graziano Pravadelli
2018	A	`conf`	Vulnerability-tolerant secure architectures. ICCAD Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari
2017	A	`conf`	3DFAR: A three-dimensional fabric for reliable multi-core processors. DATE Javad Bagherzadeh, Valeria Bertacco
2017	—	`conf`	AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs. ASP-DAC Biruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco
2017	Misc	`conf`	DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress). CODES+ISSS Alessandro Danese, Graziano Pravadelli, Valeria Bertacco
2017	—	`conf`	Energy efficient object detection on the mobile GP-GPU. AFRICON Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco
2017	A*	`conf`	MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation. ISCA Doowon Lee, Valeria Bertacco
2017	A*	`conf`	Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves. ISCA Ofir Weisse, Valeria Bertacco, Todd M. Austin
2017	—	`conf`	SNIFFER: A high-accuracy malware detector for enterprise-based systems. IVSW Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, Todd M. Austin, Valeria Bertacco
2016	A	`conf`	BugMD: automatic mismatch diagnosis for bug triaging. ICCAD Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia
2016	A	`conf`	Correct runtime operation for NoCs through adaptive-region protection. DATE Rawan Abdel-Khalek, Valeria Bertacco
2016	A*	`conf`	Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. DAC Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco
2016	J	`jnl`	Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults. IEEE Trans. Computers Ritesh Parikh, Valeria Bertacco
2015	—	`conf`	Highly Fault-tolerant NoC Routing with Application-aware Congestion Management. NOCS Doowon Lee, Ritesh Parikh, Valeria Bertacco
2015	C	`conf`	ItHELPS: Iterative high-accuracy error localization in post-silicon. ICCD Valeria Bertacco, Wade Bonkowski
2015	—	`conf`	NoCVision: A Network-on-Chip Dynamic Visualization Solution. NoCArc@MICRO Vaibhav Gogte, Doowon Lee, Ritesh Parikh, Valeria Bertacco
2015	Misc	`conf`	Panel: When will the cost of dependability end innovation in computer design? VTS Valeria Bertacco
2015	J	`jnl`	Post-Silicon Validation of Multiprocessor Memory Consistency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Biruk W. Mammo, Valeria Bertacco, Andrew DeOrio, Ilya Wagner
2015	A	`conf`	ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability. ISLPED Biruk Mammo, Ritesh Parikh, Valeria Bertacco
2014	A	`conf`	ArChiVED: Architectural checking via event digests for high performance validation. DATE Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco
2014	J	`jnl`	At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. IEEE Trans. Computers Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2014	A	`conf`	Brisk and limited-impact NoC routing reconfiguration. DATE Doowon Lee, Ritesh Parikh, Valeria Bertacco
2014	J	`jnl`	Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrea Pellegrini, Valeria Bertacco
2014	—	`conf`	DiAMOND: Distributed alteration of messages for on-chip network debug. NOCS Rawan Abdel-Khalek, Valeria Bertacco
2014	J	`jnl`	ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality. ACM Trans. Embed. Comput. Syst. Ritesh Parikh, Valeria Bertacco
2014	A	`conf`	High-radix on-chip networks with low-radix routers. ICCAD Animesh Jain, Ritesh Parikh, Valeria Bertacco
2014	J	`jnl`	Post-silicon platform for the functional diagnosis and debug of networks-on-chip. ACM Trans. Embed. Comput. Syst. Rawan Abdel-Khalek, Valeria Bertacco
2014	A*	`conf`	Power-Aware NoCs through Routing and Topology Reconfiguration. DAC Ritesh Parikh, Reetuparna Das, Valeria Bertacco
2013	—	`conf`	Cobra: A comprehensive bundle-based reliable architecture. ICSAMOS Andrea Pellegrini, Valeria Bertacco
2013	—	`ed.`	Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings Haifa Verification Conference Valeria Bertacco, Axel Legay
2013	A	`conf`	Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. ICCAD Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco
2013	A	`conf`	Machine learning-based anomaly detection for post-silicon bug diagnosis. DATE Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco
2013	A	`conf`	On the use of GP-GPUs for accelerating compute-intensive EDA applications. DATE Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel
2013	A	`conf`	Schnauzer: scalable profiling for likely security bug sites. CGO William Arthur, Biruk Mammo, Ricardo Rodríguez Jorge, Todd M. Austin, Valeria Bertacco
2013	A*	`conf`	uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults. MICRO Ritesh Parikh, Valeria Bertacco
2012	J	`jnl`	A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David T. Blaauw, Jin Hu, Gregory K. Chen
2012	A	`conf`	Approximating checkers for simulation acceleration. DATE Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco
2012	—	`conf`	Architectural Trace-Based Functional Coverage for Multiprocessor Verification. MTV Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco
2012	A	`conf`	Bridging pre- and post-silicon debugging with BiPeD. ICCAD Andrew DeOrio, Jialin Li, Valeria Bertacco
2012	A*	`conf`	Checking architectural outputs instruction-by-instruction on acceleration platforms. DAC Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco
2012	Misc	`conf`	Comprehensive online defect diagnosis in on-chip networks. VTS Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco
2012	A	`conf`	CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. DATE Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco
2012	A	`conf`	Functional post-silicon diagnosis and debug for networks-on-chip. ICCAD Rawan Abdel-Khalek, Valeria Bertacco
2012	A*	`conf`	Humans for EDA and EDA for humans. DAC Valeria Bertacco
2012	A*	`conf`	SAGA: SystemC acceleration on GPU architectures. DAC Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi
2012	Misc	`conf`	SystemC simulation on GP-GPUs: CUDA vs. OpenCL. CODES+ISSS Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee
2012	A*	`conf`	Viper: Virtual pipelines for enhanced reliability. ISCA Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco
2011	—	`conf`	A distributed and topology-agnostic approach for on-line NoC testing. NOCS Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2011	B	`conf`	ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco
2011	—	`conf`	Cardio: Adaptive CMPs for reliability through dynamic introspective operation. HLDVT Andrea Pellegrini, Valeria Bertacco
2011	A*	`conf`	DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. DAC Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh
2011	A*	`conf`	Formally enhanced runtime verification to ensure NoC functional correctness. MICRO Ritesh Parikh, Valeria Bertacco
2011	C	`conf`	Functional correctness for CMP interconnects. ICCD Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco
2011	J	`jnl`	Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
2011	A	`conf`	Highly scalable distributed dataflow analysis. CGO Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco
2011	A	`conf`	Post-silicon bug diagnosis with inconsistent executions. ICCAD Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco
2011	A	`conf`	ReliNoC: A reliable network for priority-based on-chip communication. DATE Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
2011	A	`conf`	Simulation-based signal selection for state restoration in silicon debug. ICCAD Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco
2010	A	`conf`	Application-Aware diagnosis of runtime hardware faults. ICCAD Andrea Pellegrini, Valeria Bertacco
2010	A*	`conf`	Bridging pre-silicon verification and post-silicon validation. DAC Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor
2010	C	`conf`	EQUIPE: Parallel equivalence checking with GP-GPUs. ICCD Debapriya Chatterjee, Valeria Bertacco
2010	A*	`conf`	Electronic design automation for social networks. DAC Andrew DeOrio, Valeria Bertacco
2010	A	`conf`	Fault-based attack of RSA authentication. DATE Andrea Pellegrini, Valeria Bertacco, Todd M. Austin
2010	J	`jnl`	Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko
2010	—	`conf`	Post-silicon debugging for multi-core designs. ASP-DAC Valeria Bertacco
2010	C	`conf`	SoCGuard: A runtime verification solution for the functional correctness of SoCs. VLSI-SoC Rawan Abdel-Khalek, Valeria Bertacco
2010	—	`conf`	Verification Failures: What to Do When Things Go Wrong. Haifa Verification Conference Valeria Bertacco
2009	—	`conf`	09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita
2009	J	`jnl`	A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco
2009	A	`conf`	A highly resilient routing algorithm for fault-tolerant NoCs. DATE David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw
2009	—	`conf`	Activity-based refinement for abstraction-guided simulation. HLDVT Debapriya Chatterjee, Valeria Bertacco
2009	A	`conf`	Caspar: Hardware patching for multicore processors. DATE Ilya Wagner, Valeria Bertacco
2009	A	`conf`	Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2009	A*	`conf`	Dacota: Post-silicon validation of the memory subsystem in multi-core designs. HPCA Andrew DeOrio, Ilya Wagner, Valeria Bertacco
2009	A*	`conf`	Debugging strategies for mere mortals. DAC Valeria Bertacco
2009	A*	`conf`	Event-driven gate-level simulation with GP-GPUs. DAC Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
2009	—	`book`	Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2009	A	`conf`	GCS: High-performance gate-level simulation with GPGPUs. DATE Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
2009	A*	`conf`	Human computing for EDA. DAC Andrew DeOrio, Valeria Bertacco
2009	J	`jnl`	Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Des. Test Comput. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
2009	J	`jnl`	Inferno: Streamlining Verification With Inferred Semantics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen
2009	—	`conf`	PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. HLDVT J. Hao, Valeria Bertacco
2009	A*	`conf`	Vicis: a reliable network for unreliable silicon. DAC David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester
2008	J	`jnl`	Automating Postsilicon Debugging and Repair. Computer Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	C	`conf`	CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. ICCD Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin
2008	J	`jnl`	Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	A	`conf`	MCjammer: Adaptive Verification for Multi-core Designs. DATE Ilya Wagner, Valeria Bertacco
2008	J	`jnl`	Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephen Plaza, Igor L. Markov, Valeria Bertacco
2008	—	`conf`	Optimizing non-monotonic interconnect using functional simulation and logic restructuring. ISPD Stephen Plaza, Igor L. Markov, Valeria Bertacco
2008	—	`conf`	Panel: Software practices for verification/testbench management. HLDVT Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg
2008	C	`conf`	Post-silicon verification for cache coherence. ICCD Andrew DeOrio, Adam Bauserman, Valeria Bertacco
2008	A	`conf`	Random Stimulus Generation using Entropy and XOR Constraints. DATE Stephen Plaza, Igor L. Markov, Valeria Bertacco
2008	—	`conf`	Reap what you sow: spare cells for post-silicon metal fix. ISPD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	J	`jnl`	Reliable Systems on Unreliable Fabrics. IEEE Des. Test Comput. Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao
2008	C	`conf`	Reversi: Post-silicon validation system for modern microprocessors. ICCD Ilya Wagner, Valeria Bertacco
2008	J	`jnl`	SafeResynth: A new technique for physical synthesis. Integr. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	A*	`conf`	Testudo: Heavyweight security analysis via statistical sampling. MICRO Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie
2008	J	`jnl`	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ilya Wagner, Valeria Bertacco, Todd M. Austin
2007	J	`jnl`	Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
2007	—	`conf`	Automatic error diagnosis and correction for RTL designs. HLDVT Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov
2007	A	`conf`	Automating post-silicon debugging and repair. ICCAD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Chico: An On-chip Hardware Checker for Pipeline Control Logic. MTV Andrew DeOrio, Adam Bauserman, Valeria Bertacco
2007	A	`conf`	Engineering trust with semantic guardians. DATE Ilya Wagner, Valeria Bertacco
2007	—	`conf`	Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
2007	A	`conf`	Low-cost protection for SER upsets and silicon defects. DATE Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin
2007	J	`jnl`	Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ilya Wagner, Valeria Bertacco, Todd M. Austin
2007	—	`conf`	Node Mergers in the Presence of Don't Cares. ASP-DAC Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	J	`jnl`	Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Safe Delay Optimization for Physical Synthesis. ASP-DAC Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	J	`jnl`	Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2007	A*	`conf`	Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco
2006	A*	`conf`	BulletProof: a defect-tolerant CMP switch architecture. HPCA Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky
2006	—	`conf`	Depth-driven verification of simultaneous interfaces. ASP-DAC Ilya Wagner, Valeria Bertacco, Todd M. Austin
2006	—	`conf`	Distance-Guided Hybrid Verification with GUIDO. HLDVT Valeria Bertacco
2006	A	`conf`	Distance-guided hybrid verification with GUIDO. DATE Smitha Shyam, Valeria Bertacco
2006	—	`conf`	Formal verification for real-world designs. SBCCI Valeria Bertacco
2006	—	`conf`	Low maintenance verification. SBCCI Valeria Bertacco
2006	—	`book`	Scalable Hardware Verification with Symbolic Simulation. Valeria Bertacco
2006	A*	`conf`	Shielding against design flaws with field repairable control logic. DAC Ilya Wagner, Valeria Bertacco, Todd M. Austin
2006	A*	`conf`	Ultra low-cost defect protection for microprocessor pipelines. ASPLOS Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin
2006	A	`conf`	Verification through the principle of least astonishment. ICCAD Beth Isaksen, Valeria Bertacco
2005	C	`conf`	Deployment of Better Than Worst-Case Design: Solutions and Needs. ICCD Todd M. Austin, Valeria Bertacco
2005	—	`conf`	Opportunities and challenges for better than worst-case design. ASP-DAC Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge
2005	A	`conf`	Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2005	—	`conf`	STACCATO: disjoint support decompositions from BDDs through symbolic kernels. ASP-DAC Stephen Plaza, Valeria Bertacco
2005	A	`conf`	Simulation-based bug trace minimization with BMC-based refinement. ICCAD Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2005	A*	`conf`	StressTest: an automatic approach to test generation via activity monitors. DAC Ilya Wagner, Valeria Bertacco, Todd M. Austin
2004	A*	`conf`	Circuit-aware architectural simulation. DAC SeokWoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2004	A	`conf`	Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
2002	A*	`conf`	Efficient state representation for symbolic simulation. DAC Valeria Bertacco, Kunle Olukotun
2000	A	`conf`	Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long
1999	A*	`conf`	Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. DAC Valeria Bertacco, Maurizio Damiani, Stefano Quer
1997	A	`conf`	The disjunctive decomposition of logic functions. ICCAD Valeria Bertacco, Maurizio Damiani
1996	C	`conf`	Boolean Function Representation Based on Disjoint-Support Decompositions. ICCD Valeria Bertacco, Maurizio Damiani
1996	—	`conf`	Boolean Function Representation Using Parallel-Access Diagrams. Great Lakes Symposium on VLSI Valeria Bertacco, Maurizio Damiani