Valentina Ciriani

94 papers A* 4A 12B 2C 23Misc 1Journal 38Unranked 13
YearRankTypeTitle / Venue / Authors
2025 J jnl
Area-driven Boolean bi-decomposition by function approximation.
ACM Trans. Design Autom. Electr. Syst.
Anna Bernasconi, Valentina Ciriani, Jordi Cortadella, Marco Costa, Tiziano Villa
2024 J jnl
On Exploiting PSOP Decomposition for Quantum Synthesis.
WiPiEC Journal
Anna Bernasconi, Valentina Ciriani, Gianmarco Cuciniello, Asma Taheri Monfared
2024 J jnl
PSOP decomposition for EXOR-based synthesis.
it Inf. Technol.
Anna Bernasconi, Valentina Ciriani, Gianmarco Cuciniello, Asma Taheri Monfared
2024 J jnl
Qutrit representation of quantum images: new quantum ternary circuit design.
Quantum Inf. Process.
Asma Taheri Monfared, Valentina Ciriani, Majid Haghparast
2023 C conf
Compact Quantum Circuits for Dimension Reducible Functions.
DSD
Anna Bernasconi, Valentina Ciriani, Asma Taheri Monfared, Stefano Zanoni
2023 J jnl
Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder.
Quantum Inf. Process.
Asma Taheri Monfared, Valentina Ciriani, Lauri Kettunen, Majid Haghparast
2023 J jnl
Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer.
IEEE Access
Asma Taheri Monfared, Valentina Ciriani, Tommi Mikkonen, Majid Haghparast
2023 J jnl
XOR-AND-XOR Logic Forms for Autosymmetric Functions and Applications to Quantum Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anna Bernasconi, Alessandro Berti, Valentina Ciriani, Gianna M. Del Corso, Innocenzo Fulginiti
2022 A conf
ADD-based Spectral Analysis of Probing Security.
DATE
Maria Chiara Molteni, Vittorio Zaccaria, Valentina Ciriani
2022 J jnl
Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis.
IEEE Trans. Computers
Anna Bernasconi, Valentina Ciriani, Tiziano Villa
2022 J jnl
Multiplicative Complexity of XOR Based Regular Functions.
IEEE Trans. Computers
Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni
2022 A conf
On the Optimal OBDD Representation of 2-XOR Boolean Affine Spaces.
DATE
Anna Bernasconi, Valentina Ciriani, Marco Longhi
2021 C conf
A Boolean Heuristic for Disjoint SOP Synthesis.
DSD
Padmanabhan Balasubramanian, Anna Bernasconi, Valentina Ciriani, Tiziano Villa
2021 A conf
Autosymmetry of Incompletely Specified Functions.
DATE
Anna Bernasconi, Valentina Ciriani
2020 A conf
Computing the full quotient in bi-decomposition by approximation.
DATE
Anna Bernasconi, Valentina Ciriani, Jordi Cortadella, Tiziano Villa
2020 A* conf
Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security.
DAC
Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni
2020 J jnl
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices.
J. Electron. Test.
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
2019 — conf
An OBDD-Based Technique for the Efficient Synthesis of Garbled Circuits.
STM
Stelvio Cimato, Valentina Ciriani, Ernesto Damiani, Maryam Ehsanpour
2019 A conf
Approximate Logic Synthesis by Symmetrization.
DATE
Anna Bernasconi, Valentina Ciriani, Tiziano Villa
2019 J jnl
Boolean Minimization of Projected Sums of Products via Boolean Relations.
IEEE Trans. Computers
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2019 — conf
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.
LATS
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu
2019 C conf
Testability of Switching Lattices in the Cellular Fault Model.
DSD
Anna Bernasconi, Valentina Ciriani, Luca Frontini
2018 J jnl
Composition of switching lattices for regular and for decomposed functions.
Microprocess. Microsystems
Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
2018 J jnl
Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.
Microprocess. Microsystems
Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
2018 — conf
Integrated Synthesis Methodology for Crossbar Arrays.
NANOARCH
Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena-Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu
2018 C conf
Testability of Switching Lattices in the Stuck at Fault Model.
VLSI-SoC
Anna Bernasconi, Valentina Ciriani, Luca Frontini
2017 C conf
A multiple valued logic approach for the synthesis of garbled circuits.
VLSI-SoC
Stelvio Cimato, Valentina Ciriani, Ernesto Damiani, Maryam Ehsanpour
2017 C conf
Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis.
DSD
Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
2017 A conf
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance.
DATE
Mustafa Altun, Valentina Ciriani, Mehdi Baradaran Tahoori
2017 C conf
Exploiting Quantum Gates in Secure Computation.
DSD
Maryam Ehsanpour, Stelvio Cimato, Valentina Ciriani, Ernesto Damiani
2017 J jnl
Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocess. Microsystems
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2016 J jnl
Index-Resilient Zero-Suppressed BDDs: Definition and Operations.
ACM Trans. Design Autom. Electr. Syst.
Anna Bernasconi, Valentina Ciriani
2016 C conf
Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.
DSD
Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
2016 C conf
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
DSD
Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori
2016 C conf
Synthesis on switching lattices of Dimension-reducible Boolean functions.
VLSI-SoC
Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
2015 C conf
Bi-Decomposition Using Boolean Relations.
DSD
Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2015 C conf
Biconditional-BDD Ordering for Autosymmetric Functions.
DSD
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco
2015 J jnl
On the error resilience of ordered binary decision diagrams.
Theor. Comput. Sci.
Anna Bernasconi, Valentina Ciriani, Lorenzo Lago
2015 J jnl
Using Flexibility in P-Circuits by Boolean Relations.
IEEE Trans. Computers
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2014 C conf
2-SPP Approximate Synthesis for Error Tolerant Applications.
DSD
Anna Bernasconi, Valentina Ciriani
2014 J jnl
Autosymmetric and Dimension Reducible Multiple-Valued Functions.
J. Multiple Valued Log. Soft Comput.
Anna Bernasconi, Valentina Ciriani
2014 J jnl
On the Error Resilience of Ordered Binary Decision Diagrams.
CoRR
Anna Bernasconi, Valentina Ciriani, Lorenzo Lago
2014 — conf
Radiation-tolerant standard cell synthesis using double-rail redundant approach.
ICECS
Valentina Ciriani, Luca Frontini, Valentino Liberali, Seyedruhollah Shojaii, Alberto Stabile, Gabriella Trucco
2014 — conf
Zero-Suppressed Binary Decision Diagrams Resilient to Index Faults.
IFIP TCS
Anna Bernasconi, Valentina Ciriani
2013 J jnl
Compact DSOP and Partial DSOP Forms.
Theory Comput. Syst.
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2013 C conf
Error resilient OBDDs.
DDECS
Anna Bernasconi, Valentina Ciriani, Lorenzo Lago
2013 C conf
Minimization of EP-SOPs via Boolean relations.
VLSI-SoC
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2013 A conf
Minimization of P-circuits using Boolean relations.
DATE
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2013 J jnl
SOP restructuring by exploiting don't cares.
Microprocess. Microsystems
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2012 J jnl
An OBDD approach to enforce confidentiality and visibility constraints in data publishing.
J. Comput. Secur.
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Giovanni Livraga, Pierangela Samarati
2012 J jnl
Compact DSOP and partial DSOP Forms
CoRR
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2012 C conf
Projected Don't Cares.
DSD
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2012 J jnl
Synthesis of P-circuits for logic restructuring.
Integr.
Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa
2011 — conf
An approximation algorithm for cofactoring-based synthesis.
ACM Great Lakes Symposium on VLSI
Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa
2011 — conf
Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization.
ISMVL
Anna Bernasconi, Valentina Ciriani
2011 — conf
Compact and Testable Circuits for Regular Functions.
ARCS Workshops
Anna Bernasconi, Valentina Ciriani
2011 J jnl
Dimension-reducible Boolean functions based on affine spaces.
ACM Trans. Design Autom. Electr. Syst.
Anna Bernasconi, Valentina Ciriani
2011 B conf
Enforcing Confidentiality and Data Visibility Constraints: An OBDD Approach.
DBSec
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Giovanni Livraga, Pierangela Samarati
2011 J jnl
Selective data outsourcing for enforcing privacy.
J. Comput. Secur.
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2010 J jnl
Combining fragmentation and encryption to protect privacy in data storage.
ACM Trans. Inf. Syst. Secur.
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2010 Misc conf
Fun at a Department Store: Data Mining Meets Switching Theory.
FUN
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2010 C conf
Logic synthesis and testability of D-reducible functions.
VLSI-SoC
Anna Bernasconi, Valentina Ciriani
2009 B conf
Enforcing Confidentiality Constraints on Sensitive Databases with Lightweight Trusted Clients.
DBSec
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2009 A conf
Fragmentation Design for Efficient Query Execution over Sensitive Distributed Databases.
ICDCS
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2009 A conf
Keep a Few: Outsourcing Data While Maintaining Confidentiality.
ESORICS
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2009 C conf
Logic Minimization and Testability of 2SPP-P-Circuits.
DSD
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2009 A conf
On decomposing Boolean functions via extended cofactoring.
DATE
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2008 — conf
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint.
PATMOS
Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco
2008 J jnl
Logic Minimization and Testability of 2-SPP Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
2008 C conf
On Projecting Sums of Products.
DSD
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2008 J jnl
On the construction of small fully testable circuits with low depth.
Microprocess. Microsystems
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2008 J jnl
Synthesis of Autosymmetric Functions in a New Three-Level Form.
Theory Comput. Syst.
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2008 J jnl
The optimization of kEP-SOPs: Computational complexity, approximability and experiments.
ACM Trans. Design Autom. Electr. Syst.
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2007 J jnl
A data structure for a sequence of string accesses in external memory.
ACM Trans. Algorithms
Valentina Ciriani, Paolo Ferragina, Fabrizio Luccio, S. Muthukrishnan
2007 — conf
An approximation algorithm for fully testable kEP-SOP networks.
ACM Great Lakes Symposium on VLSI
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2007 A conf
Fragmentation and Encryption to Enforce Privacy in Data Storage.
ESORICS
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati
2007 — ch.
Microdata Protection.
Secure Data Management in Decentralized Systems
Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Pierangela Samarati
2007 C conf
On the Construction of Small Fully Testable Circuits with Low Depth.
DSD
Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2006 C conf
DRedSOP: Synthesis of a New Class of Regular Functions.
DSD
Anna Bernasconi, Valentina Ciriani
2006 C conf
EXOR Projected Sum of Products.
VLSI-SoC
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2006 A conf
Efficient minimization of fully testable 2-SPP networks.
DATE
Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
2006 J jnl
Exploiting Regularities for Boolean Function Synthesis.
Theory Comput. Syst.
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2006 — conf
Logic Synthesis of EXOR Projected Sum of Products.
VLSI-SoC (Selected Papers)
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
2006 J jnl
Testability of SPP Three-Level Logic Networks in Static Fault Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2004 J jnl
Room allocation: a polynomial subcase of the quadratic assignment problem.
Discret. Appl. Math.
Valentina Ciriani, Nadia Pisanti, Anna Bernasconi
2003 — conf
Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
VLSI-SoC (Selected Papers)
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2003 J jnl
Synthesis of SPP three-level logic networks using affine spaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Valentina Ciriani
2003 J jnl
Synthesis of integer multipliers in sum of pseudoproducts form.
Integr.
Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2003 C conf
Testability of SPP Three-Level Logic Networks.
VLSI-SOC
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2003 J jnl
Three-level logic minimization based on function regularities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2002 A* conf
Fast three-level logic minimization based on autosymmetry.
DAC
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2002 — conf
Implicit Test of Regularity for Not Completely Specified Boolean Functions.
IWLS
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
2002 A* conf
Static Optimality Theorem for External Memory String Access.
FOCS
Valentina Ciriani, Paolo Ferragina, Fabrizio Luccio, S. Muthukrishnan
2001 A* conf
Logic Minimization using Exclusive OR Gates.
DAC
Valentina Ciriani