Valentin Tihhomirov

11 papers B 2C 2Journal 2Unranked 5

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
2016	—	`conf`	Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
2015	—	`conf`	Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls
2014	J	`jnl`	Automated Design Error Localization in RTL Designs. IEEE Des. Test Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2014	B	`conf`	Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
2013	—	`conf`	Assessment of diagnostic test for automated bug localization. LATW Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2012	C	`conf`	A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov
2012	—	`conf`	Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2012	—	`conf`	PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov
2005	C	`conf`	Improved Fault Emulation for Synchronous Sequential Circuits. DSD Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
2004	B	`conf`	Evaluating Fault Emulation on FPGA. FPL Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe