Valentin Puente

54 papers A* 6A 8B 4C 5Journal 23Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Efficient Server Consolidation through a balanced mix of Transformer-based and Conventional Applications. ICS Pablo Abad, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2023	B	`conf`	Performance Characterization of Popular DNN Models on Out-of-Order CPUs. PACT Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2022	A	`conf`	Top-Down Performance Profiling on NVIDIA's GPUs. IPDPS Alvaro Saiz, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2021	J	`jnl`	Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking. IEEE Trans. Parallel Distributed Syst. Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2020	J	`jnl`	Rainbow: A Composable Coherence Protocol for Multi-Chip Servers. CoRR Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2020	J	`jnl`	Rainbow: A composable coherence protocol for multi-chip servers. Concurr. Comput. Pract. Exp. Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2020	B	`conf`	SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads. ICPP Pablo Prieto, Pablo Abad Fidalgo, Jose Angel Herrero, José-Ángel Gregorio, Valentin Puente
2019	J	`jnl`	Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation. CoRR Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2019	A	`conf`	Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. IPDPS Adrian Colaso, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2019	J	`jnl`	CLASSIC: A cortex-inspired hardware accelerator. J. Parallel Distributed Comput. Valentin Puente, José-Ángel Gregorio
2018	J	`jnl`	Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation. IEEE Trans. Parallel Distributed Syst. Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2018	J	`jnl`	Mosaic: A Scalable Coherence Protocol. Int. J. Parallel Program. Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
2017	J	`jnl`	An adaptive cache coherence protocol: Trading storage for traffic. J. Parallel Distributed Comput. Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2016	J	`jnl`	AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory. IEEE Trans. Parallel Distributed Syst. Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2016	J	`jnl`	CLAASIC: a Cortex-Inspired Hardware Accelerator. CoRR Valentin Puente, José-Ángel Gregorio
2015	A*	`conf`	Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability. HPCA Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2015	J	`jnl`	Improving last level shared cache performance through mobile insertion policies (MIP). Parallel Comput. Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2014	A*	`conf`	3D stacking of high-performance processors. HPCA Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, Eren Kursun
2013	A	`conf`	CMP off-chip bandwidth scheduling guided by instruction criticality. ICS Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2013	C	`conf`	Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. DSD Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
2013	J	`jnl`	LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors. ACM Trans. Archit. Code Optim. Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2013	B	`conf`	The case for a scalable coherence protocol for complex on-chip cache hierarchies in many-core systems. PACT Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2012	J	`jnl`	Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate. IEEE Trans. Parallel Distributed Syst. Pablo Abad Fidalgo, Valentin Puente, Lucia G. Menezo, José-Ángel Gregorio
2012	C	`conf`	BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. ICCD Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2012	J	`jnl`	Balancing Performance and Cost in CMP Interconnection Networks. IEEE Trans. Parallel Distributed Syst. Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2012	—	`conf`	Improving coherence protocol reactiveness by trading bandwidth for latency. Conf. Computing Frontiers Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
2012	J	`jnl`	LOCKE Detailed Specification Tables CoRR Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2012	—	`conf`	TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. NOCS Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
2012	J	`jnl`	The Necessity for Hardware QoS Support for Server Consolidation and Cloud Computing CoRR Javier Merino, Valentin Puente, José-Ángel Gregorio
2011	J	`jnl`	Multilevel Cache Modeling for Chip-Multiprocessor Systems. IEEE Comput. Archit. Lett. Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2010	A*	`conf`	ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture. HPCA Javier Merino, Valentin Puente, José-Ángel Gregorio
2009	A*	`conf`	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. HPCA Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2008	J	`jnl`	Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology. IEEE Trans. Computers Valentin Puente, José-Ángel Gregorio, Fernando Vallejo, Ramón Beivide
2008	—	`conf`	Reducing the Interconnection Network Cost of Chip Multiprocessors. NOCS Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2008	J	`jnl`	SP-NUCA: a cost effective dynamic non-uniform cache architecture. SIGARCH Comput. Archit. News Javier Merino, Valentin Puente, Pablo Prieto, José-Ángel Gregorio
2007	J	`jnl`	Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks. IEEE Trans. Parallel Distributed Syst. Valentin Puente, José-Ángel Gregorio
2007	A*	`conf`	Rotary router: an efficient architecture for CMP interconnection networks. ISCA Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto
2006	J	`jnl`	High-performance adaptive routing for networks with arbitrary topology. J. Syst. Archit. Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide, Cruz Izu
2004	—	`conf`	A first glance at Kilo-instruction based multiprocessors. Conf. Computing Frontiers Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero
2004	—	`conf`	Evaluating kilo-instruction multiprocessors. WMPI Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
2004	A*	`conf`	Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. ISCA Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide
2004	—	`conf`	Load Unbalance in k-ary n-Cube Networks. Euro-Par José Miguel-Alonso, José A. Gregorio, Valentin Puente, Fernando Vallejo, Ramón Beivide
2004	C	`conf`	Simulation Methodology for Decision Support Workloads. PDP Luis A. Amigo, Valentin Puente, José-Ángel Gregorio
2003	A	`conf`	A Low Cost Fault Tolerant Packet Routing for Parallel Computers. IPDPS Valentin Puente, José A. Gregorio, Ramón Beivide, Fernando Vallejo
2003	J	`jnl`	On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. Valentin Puente, José A. Gregorio, Ramón Beivide, Cruz Izu
2002	C	`conf`	SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems. PDP Valentin Puente, José A. Gregorio, Ramón Beivide
2001	—	`conf`	A New Communication Mechanism for Cluster Computing. Euro-Par Andres Ibañez, Valentin Puente, José A. Gregorio, Ramón Beivide
2001	A	`conf`	A new routing mechanism for networks with irregular topology. SC Valentin Puente, José A. Gregorio, Ramón Beivide, Fernando Vallejo, Andres Ibañez
2001	J	`jnl`	The Adaptive Bubble Router. J. Parallel Distributed Comput. Valentin Puente, Cruz Izu, Ramón Beivide, José A. Gregorio, Fernando Vallejo, J. M. Prellezo
2000	C	`conf`	A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors. PDP Valentin Puente, J. M. Prellezo, Cruz Izu, José-Ángel Gregorio, Ramón Beivide
2000	A	`conf`	Improving parallel system performance by changing the arrangement of the network links. ICS Valentin Puente, Cruz Izu, José A. Gregorio, Ramón Beivide, J. M. Prellezo, Fernando Vallejo
1999	B	`conf`	Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. ICPP Valentin Puente, Ramón Beivide, José A. Gregorio, J. M. Prellezo, José Duato, Cruz Izu
1999	—	`conf`	Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications. Euro-Par Valentin Puente, José A. Gregorio, Cruz Izu, Ramón Beivide
1999	A	`conf`	Low-level router design and its impact on supercomputer system performance. International Conference on Supercomputing Valentin Puente, José A. Gregorio, Cruz Izu, Ramón Beivide, Fernando Vallejo