Valentin Gherman

27 papers A 6B 5C 4Misc 3Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2025 C conf
Improving Error Correction with Weak-Bit Information in Resistive Memories.
IOLTS
Valentin Gherman, Giuseppe Piccolboni, Zeev Freidin, Matan Guttman, Amir Regev, Gabriel Molas, Ishai Naveh, Bastien Giraud, Antoine Hebert, Ilan Sever
2024 Misc conf
Sequential Decoders for Binary Linear Block ECCs.
VTS
Valentin Gherman, Cyrille Laffond
2024 J jnl
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro.
IEEE J. Solid State Circuits
Bastien Giraud, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2023 — conf
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.
IMW
Bastien Giraud, Sebastien Ricavy, Yasser Moursy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Manuel Pezzin, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas
2020 A conf
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.
DATE
Valentin Gherman, Samuel Evain, Bastien Giraud
2020 J jnl
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.
J. Electron. Test.
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
2018 — conf
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.
DTIS
Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo
2018 — conf
Is aproximate computing suitable for selective hardening of arithmetic circuits?
DTIS
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
2017 A conf
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.
ITC
Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
2017 B conf
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps.
ETS
Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman
2014 J jnl
Error Correction Schemes with Erasure Information for Fast Memories.
J. Electron. Test.
Samuel Evain, Valentin Savin, Valentin Gherman
2014 C conf
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.
IOLTS
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman
2014 B conf
Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
ETS
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman
2013 B conf
Error-correction schemes with erasure information for fast memories.
ETS
Samuel Evain, Valentin Gherman
2013 J jnl
Memory Reliability Improvement Based on Maximized Error-Correcting Codes.
J. Electron. Test.
Valentin Gherman, Samuel Evain, Yannick Bonhomme
2013 A conf
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
DATE
Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman
2012 B conf
Memory reliability improvements based on maximized error-correcting codes.
ETS
Valentin Gherman, Samuel Evain, Yannick Bonhomme
2011 A conf
Error prediction based on concurrent self-test and reduced slack time.
DATE
Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme
2011 C conf
Generalized parity-check matrices for SEC-DED codes with fixed parity.
IOLTS
Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme
2011 Misc conf
Programmable extended SEC-DED codes for memory errors.
VTS
Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme
2010 C conf
Programmable restricted SEC codes to mask permanent faults in semiconductor memories.
IOLTS
Samuel Evain, Yannick Bonhomme, Valentin Gherman
2009 A conf
System-level hardware-based protection of memories against soft-errors.
DATE
Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme
2007 J jnl
Deterministic logic BIST for transition fault testing.
IET Comput. Digit. Tech.
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
2007 — conf
Synthesis of irregular combinational functions with large don't care sets.
ACM Great Lakes Symposium on VLSI
Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
2006 B conf
Deterministic Logic BIST for Transition Fault Testing.
ETS
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
2005 Misc conf
Implementing a Scheme for External Deterministic Self-Test.
VTS
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
2004 A conf
Efficient Pattern Mapping for Deterministic Logic BIST.
ITC
Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers