Valavan Manohararajah

12 papers A* 1A 2B 3Journal 4Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	SD CoRR Mike Lasby, Nish Sinnadurai, Valavan Manohararajah, Sean Lie, Vithursan Thangarasa
2016	A	`conf`	The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
2007	J	`jnl`	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	B	`conf`	Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006	—	`conf`	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	J	`jnl`	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006	A	`conf`	Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2005	A*	`conf`	Incremental retiming for FPGA physical synthesis. DAC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2005	B	`conf`	Post-Placement BDD-Based Decomposition for FPGAs. FPL Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
2005	—	`conf`	Two-stage physical synthesis for FPGAs. CICC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2002	B	`conf`	Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
1997	J	`jnl`	Rajah: The Design of a Chess Program. ICCA J. Valavan Manohararajah