Vaishnav Srinivas

16 papers A* 1A 3C 2Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Abinash Roy, Mahalingam Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2021 A* conf
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping.
DAC
Rassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2020 J jnl
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Aditya Narayan, Vaishnav Srinivas
2020 C conf
Graph-Based Power Network Routing for Board-Level High Performance Systems.
ISCAS
Rassul Bairamkulov, Eby G. Friedman, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas
2020 J jnl
Power Delivery Exploration Methodology Based on Constrained Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Kan Xu, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas, Eby G. Friedman
2019 — —
Cross-Layer Pathfinding for Off-Chip Interconnects
Vaishnav Srinivas
2019 — conf
Learning-based prediction of package power delivery network quality.
ASP-DAC
Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu
2018 A conf
A cross-layer methodology for design and optimization of networks in 2.5D systems.
ICCAD
Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas
2018 C conf
Versatile Framework for Power Delivery Exploration.
ISCAS
Rassul Bairamkulov, Kan Xu, Eby G. Friedman, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas
2017 J jnl
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
José L. Abellán, Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Cristian Morales, John Recchio, Vaishnav Srinivas, Tiansheng Zhang
2017 J jnl
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
ACM Trans. Archit. Code Optim.
Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
2016 A conf
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems.
DATE
Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang
2015 J jnl
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models.
IEEE Trans. Very Large Scale Integr. Syst.
Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2015 — conf
Clock clustering and IO optimization for 3D integration.
SLIP
Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas
2012 A conf
CACTI-IO: CACTI with off-chip power-area-timing models.
ICCAD
Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2011 — conf
Mobile system considerations for SDRAM interface trends.
SLIP
Andrew B. Kahng, Vaishnav Srinivas