Vaibhav Verma - RankMe

12 papers A* 2Misc 1Journal 3Unranked 6

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units. ACM Great Lakes Symposium on VLSI Xiaotian Zhao, Yimin Gao, Vaibhav Verma, Ruge Xu, Mircea Stan, Xinfei Guo
2023	—	`conf`	LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores. SOCC Yimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma, Xinfei Guo, Mircea Stan
2022	J	`jnl`	EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT. Sustain. Comput. Informatics Syst. Vaibhav Verma, Tommy Tracy II, Mircea R. Stan
2021	—	`conf`	ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge. WF-IoT Mohammad Nazmus Sakib, Rahul Sreekumar, Vaibhav Verma, Tommy Tracy II, Mircea R. Stan
2020	—	`conf`	Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. VDAT Vaibhav Verma, Fiza Akhtar, Anuj Grover
2019	J	`jnl`	A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. IEEE Comput. Archit. Lett. Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron
2019	A*	`conf`	eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing. MICRO Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron
2018	A*	`conf`	SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. DAC Yunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, Xuan Zhang
2018	—	`conf`	When "things" get older: Exploring circuit aging in IoT applications. ISQED Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea R. Stan
2017	J	`jnl`	Back to the Future: Digital Circuit Design in the FinFET Era. J. Low Power Electron. Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, Mircea R. Stan
2015	—	`conf`	A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. SoCC Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain
2014	Misc	`conf`	A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. VLSID Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja