V. Visvanathan

47 papers A* 2A 2C 2Misc 17Journal 18Unranked 6

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
2014	Misc	`conf`	ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
2013	J	`jnl`	Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
2012	J	`jnl`	Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
2010	J	`jnl`	Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
2008	J	`jnl`	Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electron. Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
2008	—	`conf`	Within-die gate delay variability measurement using re-configurable ring oscillator. CICC Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan
2005	—	`conf`	A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. ISQED Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan
2005	Misc	`conf`	Application of Alpha Power Law Models to PLL Design Methodology. VLSI Design B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni
2005	Misc	`conf`	Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. VLSI Design Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney
2001	J	`jnl`	CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pradip Mandal, V. Visvanathan
2000	J	`jnl`	Reconfigurable Filter Coprocessor Architecture for DSP Applications. J. VLSI Signal Process. S. Ramanathan, S. K. Nandy, V. Visvanathan
1999	Misc	`conf`	A New Approach for CMOS Op-Amp Synthesis. VLSI Design Pradip Mandal, V. Visvanathan
1999	J	`jnl`	A computational engine for multirate FIR digital filtering. Signal Process. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	J	`jnl`	Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. J. VLSI Signal Process. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	C	`conf`	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD Avinash K. Gautam, V. Visvanathan, S. K. Nandy
1999	J	`jnl`	Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. Integr. S. Ramanathan, V. Visvanathan
1999	J	`jnl`	Synthesis of ASIPs for DSP algorithms. Integr. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	Misc	`conf`	Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design S. Ramanathan, V. Visvanathan, S. K. Nandy
1997	Misc	`conf`	A Self-Biased High Performance Folded Cascode CMOS Op-Amp. VLSI Design Pradip Mandal, V. Visvanathan
1997	Misc	`conf`	Low-Power Configurable Processor Array for DLMS Adaptive Filtering. VLSI Design S. Ramanathan, V. Visvanathan
1996	Misc	`conf`	A systolic architecture for LMS adaptive filtering with minimal adaptation delay. VLSI Design S. Ramanathan, V. Visvanathan
1996	Misc	`conf`	Design of high performance two stage CMOS cascode op-amps with stable biasing. VLSI Design Pradip Mandal, V. Visvanathan
1996	Misc	`conf`	VLSI Implementation of DSP Architectures. VLSI Design A. Ratan Gupta, V. Visvanathan
1995	Misc	`conf`	A modular systolic architecture for delayed least mean squares adaptive filtering. VLSI Design V. Visvanathan, S. Ramanathan
1994	Misc	`conf`	A CORDIC Based Programmable DXT Processor Array. VLSI Design V. K. Anuradha, V. Visvanathan
1994	Misc	`conf`	High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
1993	J	`jnl`	A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. Very Large Scale Integr. Syst. Dinesh Somasekhar, V. Visvanathan
1993	Misc	`conf`	A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design Dinesh Somasekhar, V. Visvanathan
1993	Misc	`conf`	A Methodology for Generating Application Specific Tree Multipliers. VLSI Design S. Ramanathan, Nibedita Mohanty, V. Visvanathan
1993	—	`conf`	A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
1993	Misc	`conf`	An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. VLSI Design V. Visvanathan, Nibedita Mohanty, S. Ramanathan
1993	A	`conf`	Macromodeling of the A.C. characteristics of CMOS Op-amps. ICCAD Pradip Mandal, V. Visvanathan
1993	Misc	`conf`	NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
1993	—	`conf`	Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors. ICPP (3) Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
1991	—	`conf`	Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors. ICPP (3) Kalluri Eswar, P. Sadayappan, V. Visvanathan
1989	A*	`conf`	A Framework for Scheduling Multi-Rate Circuit Simulation. DAC Antony P.-C. Ng, V. Visvanathan
1989	J	`jnl`	Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Linda S. Milor, V. Visvanathan
1989	A*	`conf`	Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. DAC P. Sadayappan, V. Visvanathan
1989	J	`jnl`	Efficient sparse matrix factorization for circuit simulation on vector supercomputers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. P. Sadayappan, V. Visvanathan
1988	J	`jnl`	Circuit Simulation on Shared-Memory Multiprocessors. IEEE Trans. Computers P. Sadayappan, V. Visvanathan
1988	C	`conf`	Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization. ICCD P. Sadayappan, V. Visvanathan
1988	A	`conf`	Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor. ICS P. Sadayappan, V. Visvanathan
1986	—	`conf`	An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. SCG V. Visvanathan, Linda S. Milor
1984	J	`jnl`	A Computational Approach for the Diagnosability of Dynamical Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
1981	J	`jnl`	Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case. IEEE Trans. Computers V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
1981	J	`jnl`	Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems. IEEE Trans. Computers Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan