V. S. Kanchana Bhaaskaran

27 papers Misc 2Journal 14Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Unified Security Framework Using Device-Specific Fingerprint: Mitigating Hardware Trojans and Authenticating Firmware Updates. IEEE Access Hemavathy Sriramulu, Kokila Jagadeesh, V. S. Kanchana Bhaaskaran
2024	J	`jnl`	Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing. J. Supercomput. Hemavathy Sriramulu, J. Kokila, V. S. Kanchana Bhaaskaran
2023	J	`jnl`	Arbiter PUF - A Review of Design, Composition, and Security Aspects. IEEE Access Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran
2022	J	`jnl`	Lightweight VLSI Architectures for Image Encryption Applications. Int. J. Inf. Secur. Priv. Prathiba Ashok, Suyash Vardhan Srivathshav, E. Ramkumar, P. Rajkamal, V. S. Kanchana Bhaaskaran
2021	—	`conf`	Double Edge-Triggered Tristate Flip-Flop Physical Unclonable Function for Secure IoT Ecosystem. iSES Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran
2020	J	`jnl`	Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures. J. Circuits Syst. Comput. Bhuvana B. P., V. S. Kanchana Bhaaskaran
2020	—	`conf`	Borrow Select Subtractor for Low Power and Area Efficiency. ISVLSI Keshav Govindarajan, V. S. Kanchana Bhaaskaran
2020	—	`conf`	Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). iSES E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran
2020	—	`conf`	Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function. iSES Hemavathy Sriramulu, V. S. Kanchana Bhaaskaran
2019	—	`conf`	Design and Analysis of FinFET Based CSCPAL Low Power Adder. iSES Jayashree K. G, Lois Priscilla S, Bhuvana B. P., V. S. Kanchana Bhaaskaran
2019	J	`jnl`	Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit. IET Circuits Devices Syst. A. Anita Angeline, V. S. Kanchana Bhaaskaran
2019	J	`jnl`	Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. Microelectron. J. Bhuvana B. P., V. S. Kanchana Bhaaskaran
2018	J	`jnl`	Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL). J. Circuits Syst. Comput. P. Sasipriya, V. S. Kanchana Bhaaskaran
2018	—	`conf`	Energy Recovery Circuit Design for Low Power VLSI. iSES V. S. Kanchana Bhaaskaran
2018	Misc	`conf`	Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack. VLSID Bhuvana B. P., V. S. Kanchana Bhaaskaran
2017	J	`jnl`	Design and Implementation of 32-Bit High Valency Jackson Adders. J. Circuits Syst. Comput. N. Poornima, V. S. Kanchana Bhaaskaran
2017	J	`jnl`	Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique. J. Circuits Syst. Comput. Saroja S. Bhusare, V. S. Kanchana Bhaaskaran
2016	J	`jnl`	Low Power, High Speed and Area Efficient Binary Count Multiplier. J. Circuits Syst. Comput. Kore Sagar Dattatraya, Ritesh Belgudri, Ramdas Bhanudas Khaladkar, V. S. Kanchana Bhaaskaran
2015	—	`conf`	Gating techniques for 6T SRAM cell using different modes of FinFET. ICACCI Deeksha Anandani, Anurag Kumar, V. S. Kanchana Bhaaskaran
2015	—	`conf`	Two phase sinusoidal power clocked quasi-static adiabatic logic families. IC3 P. Sasipriya, V. S. Kanchana Bhaaskaran
2014	—	`conf`	Design and analysis of program counter using finite state machine and incrementer based logic. ICACCI M. Divya, Ritesh Belgudri, V. S. Kanchana Bhaaskaran
2014	—	`conf`	Low power divider using vedic mathematics. ICACCI Dalal Rutwik Kishor, V. S. Kanchana Bhaaskaran
2014	—	`conf`	Low power vedic multiplier using energy recovery logic. ICACCI Hardik Sangani, Tanay M. Modi, V. S. Kanchana Bhaaskaran
2012	J	`jnl`	Pre-Resolve and Sense Adiabatic Logic for 100 kHz to 500 MHz Frequency Classes. J. Circuits Syst. Comput. V. S. Kanchana Bhaaskaran, J. P. Raina
2010	J	`jnl`	Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. J. Circuits Syst. Comput. V. S. Kanchana Bhaaskaran, J. P. Raina
2008	J	`jnl`	Differential Cascode Adiabatic Logic Structure for Low Power. J. Low Power Electron. V. S. Kanchana Bhaaskaran, J. P. Raina
2006	Misc	`conf`	Semi-Custom Design of Adiabatic Adder Circuits. VLSI Design V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel