V. R. Devanathan

26 papers A 8Misc 7Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2016	A	`conf`	A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. ITC V. R. Devanathan, Sumant Kale
2015	J	`jnl`	Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
2015	Misc	`conf`	Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSID Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti
2015	Misc	`conf`	New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. VLSID V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji
2015	J	`jnl`	ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
2014	Misc	`conf`	ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
2013	J	`jnl`	Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
2013	A	`conf`	Towards adaptive test of multi-core RF SoCs. DATE Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji
2012	J	`jnl`	Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
2011	Misc	`conf`	Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. VLSI Design V. R. Devanathan, Ishaan Santhosh Shah
2011	—	`conf`	Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. Asian Test Symposium V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra
2011	A	`conf`	Techniques to improve memory interface test quality for complex SoCs. ITC V. R. Devanathan, Srinivas Kumar Vooka
2010	J	`jnl`	EOMP: an exactly once multicast protocol for distributed mobile systems. Int. J. Parallel Emergent Distributed Syst. M. A. Maluk Mohamed, V. R. Devanathan, D. Janakiram
2010	A	`conf`	Towards effective and compression-friendly test of memory interface logic. ITC V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar
2008	J	`jnl`	A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2007	A	`conf`	A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	Misc	`conf`	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	A	`conf`	Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	A	`conf`	Methodology for low power test pattern generation using activity threshold control logic. ICCAD Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
2007	A	`conf`	PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2007	Misc	`conf`	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	J	`jnl`	Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2006	J	`jnl`	On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2005	Misc	`conf`	A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
2005	—	`conf`	Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. Asian Test Symposium V. R. Devanathan
2003	—	`conf`	A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems. ICDCS Workshops D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan