V. Kamakoti - RankMe

110 papers A 15B 7Misc 24Journal 43Unranked 21

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. IEEE Trans. Dependable Secur. Comput. Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti
2023	A	`conf`	YODA: Covert Communication Channel over Public DNS Resolvers. DSN Sandip Saha, Sareena Karapoola, Chester Rebeiro, V. Kamakoti
2023	—	`conf`	iPyrDAE: Image Pyramid-Based Denoising Autoencoder for Infrared Breast Images. PReMI Kaushik Raghavan, B. Sivaselavan, V. Kamakoti
2022	J	`jnl`	FadingBF: A Bloom Filter With Consistent Guarantees for Online Applications. IEEE Trans. Computers Prasanna Karthik Vairam, Pratyush Kumar, Chester Rebeiro, V. Kamakoti
2022	A	`conf`	RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks. CIKM Sareena Karapoola, Nikhilesh Singh, Chester Rebeiro, V. Kamakoti
2022	J	`jnl`	Snoopy: A Webpage Fingerprinting Framework with Finite Query Model for Mass-Surveillance. CoRR Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti
2021	J	`jnl`	PERI: A Configurable Posit Enabled RISC-V Core. ACM Trans. Archit. Code Optim. Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti
2019	A	`conf`	Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. ICCAD Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti
2019	J	`jnl`	PERI: A Posit Enabled RISC-V Core. CoRR Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti
2019	J	`jnl`	PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks. IEEE Trans. Cogn. Commun. Netw. Milan Patnaik, V. Kamakoti, Vashek Matyas, Vojtech Rehák
2018	J	`jnl`	An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. ACM J. Emerg. Technol. Comput. Syst. Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti
2018	J	`jnl`	MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. J. Low Power Electron. Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti
2017	—	`conf`	A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. DFT Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri
2017	J	`jnl`	Approximate Error Detection With Stochastic Checkers. IEEE Trans. Very Large Scale Integr. Syst. Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
2016	Misc	`conf`	ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. VLSID Vikas Chauhan, Neel Gala, V. Kamakoti
2016	Misc	`ed.`	Information Systems Security - 12th International Conference, ICISS 2016, Jaipur, India, December 16-20, 2016, Proceedings ICISS Indrajit Ray, Manoj Singh Gaur, Mauro Conti, Dheeraj Sanghi, V. Kamakoti
2016	J	`jnl`	ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks. Comput. Commun. N. Sathya Narayanan, Milan Patnaik, V. Kamakoti
2016	Misc	`conf`	SHAKTI Processors: An Open-Source Hardware Initiative. VLSID Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti
2016	A	`conf`	STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. ISLPED Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
2015	J	`jnl`	Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
2015	J	`jnl`	DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan
2015	A	`conf`	DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. DATE Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti
2015	Misc	`conf`	Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSID Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti
2015	J	`jnl`	Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization. Appl. Soft Comput. L. Srivani, N. H. V. Krishna Giri, Shankar Ganesh, V. Kamakoti
2015	J	`jnl`	ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
2015	—	`conf`	SHAKTI-F: A Fault Tolerant Microprocessor Architecture. ATS Sukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti
2014	Misc	`conf`	ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
2014	J	`jnl`	ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization. J. Low Power Electron. K. Shyamala, V. Kamakoti
2014	J	`jnl`	XStat: Statistical J. Low Power Electron. Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti
2013	J	`jnl`	A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays. ACM J. Emerg. Technol. Comput. Syst. Shri K. V. Srinivasan, V. Kamakoti, A. Bhattacharya
2013	J	`jnl`	An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. J. Low Power Electron. Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti
2013	B	`conf`	PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. ETS Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti
2013	J	`jnl`	Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
2012	J	`jnl`	A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electr. Comput. Eng. Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli
2012	J	`jnl`	Interconnect Aware Test Power Reduction. J. Low Power Electron. Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti
2012	J	`jnl`	Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
2011	—	`conf`	A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli
2011	J	`jnl`	Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. Appl. Soft Comput. Shoaib Mohammed, Sk. Noor Mahammad, V. Kamakoti
2011	—	`conf`	Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti
2011	J	`jnl`	ROSY: recovering processor and memory systems from hard errors. ACM SIGOPS Oper. Syst. Rev. Karthik Raghavan, V. Kamakoti
2011	—	`conf`	Towards Quick Solutions for Generalized Placement Problem. ISED S. Srinivasan, V. Kamakoti, A. Bhattacharya
2010	J	`jnl`	Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. Kavish Seth, V. Kamakoti, S. Srinivasan
2010	Misc	`conf`	Impact of Temperature on Test Quality. VLSI Design Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti
2009	Misc	`conf`	Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi
2009	J	`jnl`	HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. ACM SIGOPS Oper. Syst. Rev. Kunal Korgaonkar, K. George, M. Gautam, V. Kamakoti
2009	J	`jnl`	Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. J. Low Power Electron. K. Shyamala, J. Vimalkumar, V. Kamakoti
2009	J	`jnl`	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi
2008	J	`jnl`	A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2008	J	`jnl`	Automatic Constraint Based Test Generation for Behavioral HDL Models. IEEE Trans. Very Large Scale Integr. Syst. Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil
2007	J	`jnl`	A novel approach to the placement and routing problems for field programmable gate arrays. Appl. Soft Comput. Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
2007	A	`conf`	A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	J	`jnl`	Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. J. Low Power Electron. K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
2007	Misc	`conf`	Controllability-driven Power Virus Generation for Digital Circuits. VLSI Design K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
2007	J	`jnl`	FPGA based Agile Algorithm-On-Demand Co-Processor CoRR Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
2007	Misc	`conf`	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	A	`conf`	Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	A	`conf`	PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
2007	Misc	`conf`	Power Virus Generation Using Behavioral Models of Circuits. VTS K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
2007	Misc	`conf`	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2007	J	`jnl`	System-on-programmable-chip implementation for on-line face recognition. Pattern Recognit. Lett. A. Pavan Kumar, V. Kamakoti, Sukhendu Das
2007	J	`jnl`	Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2006	Misc	`conf`	An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
2006	—	`conf`	Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
2006	J	`jnl`	On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
2006	J	`jnl`	Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
2006	Misc	`conf`	Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
2005	—	`conf`	A Framework for Automatic Assembly Program Generator (A Asian Test Symposium K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil
2005	Misc	`conf`	A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. VLSI Design Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
2005	Misc	`conf`	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. VLSI Design K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti
2005	—	`conf`	A function generator-based reconfigurable system. ASP-DAC Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
2005	—	`conf`	A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
2005	—	`conf`	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
2005	Misc	`conf`	Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
2005	A	`conf`	Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
2005	A	`conf`	FPGA based Agile Algorithm-On-Demand Co-Processor. DATE Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
2005	A	`conf`	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
2005	Misc	`conf`	Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia
2005	J	`jnl`	Pseudo-online testing methodologies for various components of field programmable gate arrays. Microprocess. Microsystems L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti
2004	Misc	`conf`	A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
2004	B	`conf`	A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. ICONIP Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
2004	Misc	`conf`	A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar
2004	—	`conf`	A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan
2004	—	`conf`	An Architecture for Real Time Face Recognition Using WMPCA. ICVGIP A. Pavan Kumar, V. Kamakoti, Sukhendu Das
2004	—	`conf`	An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. MICAI Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
2004	B	`conf`	Face Recognition Using Weighted Modular Principle Component Analysis. ICONIP A. Pavan Kumar, Sukhendu Das, V. Kamakoti
2004	A	`conf`	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. IPDPS A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti
2004	B	`conf`	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. FPL R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti
2004	A	`conf`	MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. DATE A. Manoj Kumar, Jayaram Bobba, V. Kamakoti
2004	A	`conf`	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. FPGA A. Manoj Kumar, B. Jayaram, V. Kamakoti
2004	—	`conf`	SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. FPT R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti
2003	—	`conf`	A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. Asian Test Symposium L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
2003	—	`conf`	A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. IICAI Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti
2003	A	`conf`	A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. IPDPS Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
2003	B	`conf`	An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. IEEE Congress on Evolutionary Computation Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
2003	—	`conf`	Dynamic Coding Technique For Low-Power Data Bus. ISVLSI M. Madhu, V. Srinivasa Murty, V. Kamakoti
2003	—	`conf`	On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh
2003	Misc	`conf`	Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. HiPC B. Jayaram, A. Manoj Kumar, V. Kamakoti
2003	B	`conf`	Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
2002	—	`conf`	A novel three phase parallel genetic approach to routing for field programmable gate arrays. FPT Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
2001	Misc	`conf`	Toward Optimal Player Weights in Secure Distributed Protocols. INDOCRYPT K. Srinathan, C. Pandu Rangan, V. Kamakoti
1999	J	`jnl`	Adaptive finite element analysis on a parallel and distributed environment. Parallel Comput. V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti
1998	Misc	`conf`	The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. COCOON Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan
1997	Misc	`conf`	An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions. HiPC Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan
1997	B	`conf`	Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. ICPADS V. Kamakoti, N. Balakrishnan
1997	J	`jnl`	Sparse Dominance Queries for Many Points in Optimal Time and Space. Inf. Process. Lett. Thomas Graf, V. Kamakoti
1995	J	`jnl`	An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. Nord. J. Comput. V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan
1995	J	`jnl`	Efficient Parallel Algorithms for Permutation Graphs. J. Parallel Distributed Comput. K. Arvind, V. Kamakoti, C. Pandu Rangan
1995	Misc	`conf`	Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. COCOON V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan
1994	—	`conf`	Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. IFIP Congress (1) P. Jagan Mohan, V. Kamakoti, C. Pandu Rangan
1992	J	`jnl`	An Optimal Algorithm for Reconstructing a Binary Tree. Inf. Process. Lett. V. Kamakoti, C. Pandu Rangan