V. K. Tomar

12 papers Journal 9Unranked 3

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	10T SRAM cell Analysis for improved Read and Write Noise Margin. ICCCNT Saloni Bansal, V. K. Tomar
2022	J	`jnl`	Characterization of Stable 12T SRAM with Improved Critical Charge. J. Circuits Syst. Comput. Ashish Sachdeva, V. K. Tomar
2022	J	`jnl`	Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices. J. Circuits Syst. Comput. Harekrishna Kumar, V. K. Tomar
2022	J	`jnl`	Design of a soft error hardened SRAM cell with improved access time for embedded systems. Microprocess. Microsystems V. K. Tomar, Ashish Sachdeva
2021	J	`jnl`	A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications. Wirel. Pers. Commun. Ashish Sachdeva, V. K. Tomar
2021	J	`jnl`	A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era. Wirel. Pers. Commun. Harekrishna Kumar, V. K. Tomar
2021	J	`jnl`	Design of 10T SRAM cell with improved read performance and expanded write margin. IET Circuits Devices Syst. Ashish Sachdeva, V. K. Tomar
2021	J	`jnl`	Design of Low Power Half Select Free 10T Static Random-Access Memory Cell. J. Circuits Syst. Comput. Ashish Sachdeva, V. K. Tomar
2021	J	`jnl`	Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices. J. Circuits Syst. Comput. Harekrishna Kumar, V. K. Tomar
2020	J	`jnl`	Design of a Stable Low Power 11-T Static Random Access Memory Cell. J. Circuits Syst. Comput. Ashish Sachdeva, V. K. Tomar
2020	—	`conf`	Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node. ICCCNT Deepak Mittal, V. K. Tomar
2018	—	`conf`	Analysis of Cache(SRAM) Memory for Core i™ 7 Processor. ICCCNT Reeya Agrawal, V. K. Tomar