Uri C. Weiser - RankMe

58 papers A* 8B 1C 2Journal 40Unranked 7

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Enhancing DNN Computational Efficiency via Decomposition and Approximation. IEEE Access Ori Schweitzer, Uri C. Weiser, Freddy Gabbay
2023	J	`jnl`	Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture. IEEE Comput. Archit. Lett. Samer Kurzum, Gil Shomron, Freddy Gabbay, Uri C. Weiser
2021	A*	`conf`	Post-Training Sparsity-Aware Quantization. NeurIPS Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser
2021	J	`jnl`	Post-Training Sparsity-Aware Quantization. CoRR Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser
2020	J	`jnl`	A Neural Network Prefetcher for Arbitrary Memory Access Patterns. ACM Trans. Archit. Code Optim. Leeor Peled, Uri C. Weiser, Yoav Etsion
2020	A*	`conf`	Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. MICRO Gil Shomron, Uri C. Weiser
2020	J	`jnl`	Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. CoRR Gil Shomron, Uri C. Weiser
2020	J	`jnl`	Post-Training BatchNorm Recalibration. CoRR Gil Shomron, Uri C. Weiser
2020	A*	`conf`	Robust Quantization: One Model to Rule Them All. NeurIPS Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alex M. Bronstein, Uri C. Weiser
2020	J	`jnl`	Robust Quantization: One Model to Rule Them All. CoRR Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alexander M. Bronstein, Uri C. Weiser
2020	J	`jnl`	Semantic prefetching using forecast slices. CoRR Leeor Peled, Uri C. Weiser, Yoav Etsion
2020	—	`conf`	Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. ECCV (10) Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser
2019	J	`jnl`	SMT-SA: Simultaneous Multithreading in Systolic Arrays. IEEE Comput. Archit. Lett. Gil Shomron, Tal Horowitz, Uri C. Weiser
2019	J	`jnl`	Spatial Correlation and Value Prediction in Convolutional Neural Networks. IEEE Comput. Archit. Lett. Gil Shomron, Uri C. Weiser
2019	J	`jnl`	Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. CoRR Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser
2018	J	`jnl`	Exploiting Spatial Correlation in Convolutional Neural Networks for Activation Value Prediction. CoRR Gil Shomron, Uri C. Weiser
2018	J	`jnl`	Towards Memory Prefetching with Neural Networks: Challenges and Insights. CoRR Leeor Peled, Uri C. Weiser, Yoav Etsion
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	Insights from the 2016 Eckert-Mauchly Award Recipient. IEEE Micro Uri C. Weiser
2017	J	`jnl`	MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar
2017	J	`jnl`	Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser
2017	J	`jnl`	Resistive Address Decoder. IEEE Comput. Archit. Lett. Leonid Yavits, Uri C. Weiser, Ran Ginosar
2016	J	`jnl`	Convex Optimization of Real Time SoC. CoRR Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser
2016	J	`jnl`	EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2016	J	`jnl`	H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann, Yoni Aizik
2016	—	`conf`	Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question. SAMOS Uri C. Weiser
2015	J	`jnl`	Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck. IEEE Comput. Archit. Lett. Leonid Azriel, Avi Mendelson, Uri C. Weiser
2015	J	`jnl`	Power and thermal constraints of modern system-on-a-chip computer. Microelectron. J. Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser
2015	A*	`conf`	Semantic locality and context-based prefetching using reinforcement learning. ISCA Leeor Peled, Shie Mannor, Uri C. Weiser, Yoav Etsion
2014	J	`jnl`	Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. IEEE Comput. Archit. Lett. Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson
2014	—	`conf`	Energy management of highly dynamic server workloads in an heterogeneous data center. PATMOS Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar
2014	J	`jnl`	Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2014	A*	`conf`	Loop-Aware Memory Prefetching Using Code Block Working Sets. MICRO Adi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion
2014	J	`jnl`	MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014	J	`jnl`	Memristor-Based Multithreading. IEEE Comput. Archit. Lett. Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2013	J	`jnl`	Optimal Resource Allocation with MultiAmdahl. Computer Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
2013	J	`jnl`	TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2012	J	`jnl`	MultiAmdahl: How Should I Divide My Heterogenous Chip? IEEE Comput. Archit. Lett. Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
2012	J	`jnl`	Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
2011	C	`conf`	Memristor-based IMPLY logic design procedure. ICCD Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman
2011	J	`jnl`	Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments CoRR Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
2010	A*	`ed.`	37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France ISCA André Seznec, Uri C. Weiser, Ronny Ronen
2010	—	`conf`	Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
2010	C	`conf`	Threads vs. caches: Modeling the behavior of parallel workloads. ICCD Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2009	J	`jnl`	Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2009	A*	`conf`	Multiple clock and voltage domains for chip multi processors. MICRO Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser
2008	J	`jnl`	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. Very Large Scale Integr. Syst. A. Elyada, Ran Ginosar, Uri C. Weiser
2008	B	`conf`	Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2007	J	`jnl`	Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
2006	J	`jnl`	Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. IEEE Comput. Archit. Lett. Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé
2004	—	`conf`	Interconnect-power dissipation in a microprocessor. SLIP Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir
1999	A*	`conf`	Correlated Load-Address Predictors. ISCA Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser
1997	J	`jnl`	Intel MMX for Multimedia PCs. Commun. ACM Alex Peleg, Sam Wilkie, Uri C. Weiser
1997	—	`conf`	Intel's MMX™ technology-a new instruction set extension. COMPCON Oded Lempel, Alex Peleg, Uri C. Weiser
1996	J	`jnl`	MMX technology extension to the Intel architecture. IEEE Micro Alex Peleg, Uri C. Weiser
1991	—	`conf`	Efficient Systolic Array for Matrix Multiplication. ICPP (3) Fabian Klass, Uri C. Weiser