Unai Bidarte - RankMe

41 papers B 5C 4Journal 17Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Proof-Of-Concept ASIC RISC-V Based SoC for Industrial Applications. DCIS Sara Alonso, Alejandro Arteaga, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, Jose Ignacio Garate, José Ángel Araujo, Victor Martínez, Unai Bidarte, Armando Astarloa
2023	—	`conf`	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. DCIS Sara Alonso, Jesús Lázaro, Jaime Jiménez, Leire Muguira, Unai Bidarte
2022	J	`jnl`	Embedded firewall for on-chip bus transactions. Comput. Electr. Eng. Jesús Lázaro, Unai Bidarte, Leire Muguira, Armando Astarloa, Jaime Jiménez
2022	—	`conf`	The influence of virtualization on real-time systems' interrupts in embedded SoC platforms. DCIS Sara Alonso, Jesús Lázaro, Jaime Jiménez, Leire Muguira, Unai Bidarte
2021	J	`jnl`	A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. IEEE Access Mikel Rodriguez, Jesús Lázaro, Unai Bidarte, Jaime Jiménez, Armando Astarloa
2021	—	`conf`	Evaluating the OpenAMP framework in real-time embedded SoC platforms. DCIS Sara Alonso, Jesús Lázaro, Jaime Jimenez, Leire Muguira, Unai Bidarte
2021	J	`jnl`	Fast and efficient address search in System-on-a-Programmable-Chip using binary trees. Comput. Electr. Eng. Jesús Lázaro, Unai Bidarte, Leire Muguira, Carlos Cuadrado, Jaime Jiménez
2019	—	`conf`	Fast and efficient FPGA prototype system for embedded control algorithms in electric traction. DCIS Carlos Cuadrado, Iñigo Kortabarria, Jesús Lázaro, Unai Bidarte, Jaime Jiménez
2019	J	`jnl`	Smart Sensor: SoC Architecture for the Industrial Internet of Things. IEEE Internet Things J. Marcelo Urbina, Tatiana Acosta, Jesús Lázaro, Armando Astarloa, Unai Bidarte
2018	J	`jnl`	SEU emulation in industrial SoCs combining microprocessor and FPGA. Reliab. Eng. Syst. Saf. Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jaime Jimenez, Jesús Lázaro
2018	—	`conf`	System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. DCIS Mikel Rodriguez, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
2017	J	`jnl`	Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. IEEE Access Marcelo Urbina, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Igor Villalta, Mikel Rodriguez
2017	J	`jnl`	Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. Microelectron. Reliab. Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jesús Lázaro, Armando Astarloa
2017	J	`jnl`	On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. IEEE Trans. Smart Grid Naiara Moreira, Jesús Lázaro, Unai Bidarte, Jaime Jimenez, Armando Astarloa
2016	C	`conf`	Intelligent gateway for Industry 4.0-compliant production. IECON Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, Jesús Lázaro
2016	J	`jnl`	Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. Reliab. Eng. Syst. Saf. Uli Kretzschmar, Julen Gomez-Cornejo, Armando Astarloa, Unai Bidarte, Javier Del Ser
2015	—	`conf`	FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. ReConFig Armando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono
2014	B	`conf`	Fast and accurate SEU-tolerance characterization method for Zynq SoCs. FPL Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro
2013	C	`conf`	Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzschmar, Unai Bidarte, Jaime Jimenez
2013	C	`conf`	System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Mikel Idirin
2011	J	`jnl`	I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, Jaime Jimenez
2011	—	`conf`	Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. ReConFig Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez
2010	—	`conf`	An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, José Luis Martín
2010	J	`jnl`	Reconfigurable Multiprocessor Systems: A Review. Int. J. Reconfigurable Comput. Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
2009	—	`conf`	AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga
2009	—	`conf`	DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2009	—	`conf`	Overview of FPGA-Based Multiprocessor Systems. ReConFig Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa
2009	—	`conf`	PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2008	—	`conf`	Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. ReConFig Armando Astarloa, Unai Bidarte, Jesús Lázaro, Jon Andreu, José Luis Martín
2008	C	`conf`	Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ATC Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro, Iñigo Martínez de Alegría
2007	J	`jnl`	Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa, Aitzol Zuloaga
2007	J	`jnl`	Hardware architecture for a general regression neural network coprocessor. Neurocomputing Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
2007	J	`jnl`	Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
2006	J	`jnl`	Comparison of two designs for the multifunction vehicle bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
2005	J	`jnl`	Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
2005	J	`jnl`	Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
2004	B	`conf`	A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
2004	—	`conf`	Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
2004	B	`conf`	High Throughput Serpent Encryption Implementation. FPL Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
2004	B	`conf`	Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. FPL Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
2003	B	`conf`	Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría