Uming Ko - RankMe

27 papers A* 2A 6C 2Journal 7Unranked 10

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. ISSCC Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko
2016	—	`conf`	4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. ISSCC Hugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko
2016	—	`conf`	Analog-digital partitioning and coupling in 3D-IC for RF applications. 3DIC Gilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha P. Chandrakasan
2016	A	`conf`	Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs. DATE Sunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh, Anantha P. Chandrakasan
2015	—	`conf`	23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. ISSCC Hugh Mair, Gordon Gammie, Alice Wang, Sumanth Gururajarao, Ichiro Lin, HsinChen Chen, Wuan Kuo, Anand Rajagopalan, Wei-Zheng Ge, Rolf Lagerquist, Syed Rahman, C. J. Chung, Simon Wang, Lee-Kee Wong, Yi-Chang Zhuang, Kent Li, Jidong Wang, Minh Chau, Yijing Liu, Daniel Dia, Mark Peng, Uming Ko
2014	—	`conf`	10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. ISSCC Alice Wang, Tsung-Yao Lin, Shichin Ouyang, Wei-Hung Huang, Jidong Wang, Shu-Hsin Chang, Sheng-Ping Chen, Chun-Hsiung Hu, J. C. Tai, Koan-Sin Tan, Meng-Nan Tsou, Ming-Hsien Lee, Gordon Gammie, Chi-Wei Yang, Chih-Chieh Yang, Yeh-Chi Chou, Shih-Hung Lin, Wuan Kuo, Chi-Jui Chung, Lee-Kee Yong, Chia-Wei Wang, Kin Hooi Dia, Cheng-Hsing Chien, You-Ming Tsao, N. K. Singh, Rolf Lagerquist, Chih-Cheng Chen, Uming Ko
2013	—	`conf`	EP3: Empowering the killer SoC applications of 2020. ISSCC Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore
2013	J	`jnl`	Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Maurits Ortmanns, Timothy C. Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai
2012	J	`jnl`	A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
2012	A	`conf`	Ultra-low power challenges for the next generation ASIC. ISLPED Uming Ko
2011	—	`conf`	A 28nm 0.6V low-power DSP for mobile applications. ISSCC Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko
2010	J	`jnl`	SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proc. IEEE Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko
2008	—	`conf`	A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. ISSCC Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko
2007	—	`conf`	Solutions for logic and processor core design at the 45nm technology node & and below. ICECS Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko
2006	A*	`conf`	Entering the hot zone - can you handle the heat and be cool? DAC Andrew Yang, Rajit Chandra, Simon Burke, Javier A. DeLaCruz, Sribalan Santhanam, Uming Ko
2005	A*	`conf`	A design platform for 90-nm leakage reduction techniques. DAC Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko
2000	J	`jnl`	High-performance energy-efficient D-flip-flop circuits. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara
1999	C	`conf`	DSP for the Third Generation Wireless Communications. ICCD Uming Ko, Mike McMahan, Edgar Auslander
1998	J	`jnl`	Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1997	C	`conf`	A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. ICCD David Li, Andrew Pua, Pranjal Srivastava, Uming Ko
1997	A	`conf`	High-performance, low-power design techniques for dynamic to static logic interface. ISLPED June Jiang, Kan Lu, Uming Ko
1997	A	`conf`	Hybrid dual-threshold design techniques for high-performance processors with low-power features. ISLPED Uming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava
1996	A	`conf`	Design techniques for high performance, energy efficient control logic. ISLPED Uming Ko, Anthony M. Hill, Poras T. Balsara
1995	—	`conf`	Energy optimization of multi-level processor cache architectures. ISLPD Uming Ko, Poras T. Balsara, Ashwini K. Nanda
1995	J	`jnl`	Low-power design techniques for high-performance CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, T. Balsara, Wai Lee
1995	J	`jnl`	Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. Very Large Scale Integr. Syst. Uming Ko, Poras T. Balsara
1985	A	`conf`	Contactless VLSI Laser Probing. ITC Uming Ko, Dinesh G. Patel, Francois J. Henley