Ulya R. Karpuzcu

80 papers A* 15A 3C 2Misc 1Journal 49Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
Decomposing Large-Scale Ising Problems on FPGAs: A Hybrid Hardware Approach.
CoRR
Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim
2026 J jnl
Extractive summarization on a CMOS Ising machine.
CoRR
Ziqing Zeng, Abhimanyu Kumar, Ahmet Efe, Ruihong Yin, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2026 J jnl
Implicitly Parallel Neuromorphic Solver Design for Constraint Satisfaction Problems.
CoRR
Recep Bugra Uludag, Ahmet Efe, Ismail Akturk, Ulya R. Karpuzcu
2025 J jnl
DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design.
CoRR
Abhimanyu Kumar, S. Ramprasath, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2025 J jnl
On Solving Structured SAT on Ising Machines: A Semiprime Factorization Study.
CoRR
Ahmet Efe, Hüsrev Cilasun, Abhimanyu Kumar, Nafisa Sadaf Prova, Ziqing Zeng, Tahmida Islam, Ruihong Yin, Chaohui Li, Peter Kreye, Chris H. Kim, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2025 J jnl
The Case for Secure Miniservers Beyond the Edge.
IEEE Trans. Computers
Salonik Resch, Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Jianping Wang, Sachin S. Sapatnekar, Ismail Akturk, Ulya R. Karpuzcu
2024 A* conf
On Error Correction for Nonvolatile Processing-In-Memory.
ISCA
Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2024 A conf
On Gate Flip Errors in Computing-In-Memory.
DATE
Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2024 J jnl
On Heterogeneous Ising Machines.
CoRR
Hüsrev Cilasun, Abhimanyu Kumar, Ziqing Zeng, Nafisa Sadaf Prova, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2023 J jnl
3SAT on an All-to-All-Connected CMOS Ising Solver Chip.
CoRR
M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2023 A* conf
On Endurance of Processing in (Nonvolatile) Memory.
ISCA
Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2023 — conf
PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing.
ICRC
Salonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022 J jnl
Benchmarking Quantum Computers and the Impact of Quantum Noise.
ACM Comput. Surv.
Salonik Resch, Ulya R. Karpuzcu
2022 J jnl
CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM.
IEEE Trans. Emerg. Top. Comput.
Zamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022 J jnl
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions.
ACM Trans. Embed. Comput. Syst.
Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022 J jnl
Error Detection and Correction for Processing in Memory (PiM).
CoRR
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022 J jnl
GeNVoM: Read Mapping Near Non-Volatile Memory.
IEEE ACM Trans. Comput. Biol. Bioinform.
S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu
2022 J jnl
On Variable Strength Quantum ECC.
IEEE Comput. Archit. Lett.
Salonik Resch, Ulya R. Karpuzcu
2021 J jnl
A Day In the Life of a Quantum Error.
IEEE Comput. Archit. Lett.
Salonik Resch, Swamit S. Tannu, Ulya R. Karpuzcu, Moinuddin K. Qureshi
2021 — conf
CAMeleon: Reconfigurable B(T)CAM in Computational RAM.
ACM Great Lakes Symposium on VLSI
Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu
2021 J jnl
Cryogenic PIM: Challenges & Opportunities.
IEEE Comput. Archit. Lett.
Salonik Resch, M. Hüsrev Cilasun, Ulya R. Karpuzcu
2021 — conf
Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation.
SEED
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021 J jnl
Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator.
CoRR
Masoud Zabihi, Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2021 J jnl
On Value Recomputation to Accelerate Invisible Speculation.
CoRR
Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021 — conf
Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM.
SEED
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021 J jnl
Special Issue on Quantum Computing.
IEEE Micro
Ulya R. Karpuzcu
2021 J jnl
Spiking Neural Networks in Spintronic Computational RAM.
ACM Trans. Archit. Code Optim.
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021 J jnl
Towards Homomorphic Inference Beyond the Edge.
CoRR
Salonik Resch, Zamshed I. Chowdhury, M. Hüsrev Cilasun, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021 J jnl
Trading Computation for Communication: A Taxonomy of Data Recomputation Techniques.
IEEE Trans. Emerg. Top. Comput.
Ismail Akturk, Ulya R. Karpuzcu
2020 A* conf
ACR: Amnesic Checkpointing and Recovery.
HPCA
Ismail Akturk, Ulya R. Karpuzcu
2020 J jnl
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM).
CoRR
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020 A* conf
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM.
DAC
M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020 J jnl
Dual-precision fixed-point arithmetic for low-power ray-triangle intersections.
Comput. Graph.
Krishna Rajan, Soheil Hashemi, Ulya R. Karpuzcu, Michael C. Doggett, Sherief Reda
2020 A* conf
MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications.
MICRO
Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020 J jnl
PIMBALL: Binary Neural Networks in Spintronic Memory.
ACM Trans. Archit. Code Optim.
Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020 J jnl
Voltage Noise Mitigation With Barrier Approximation.
IEEE Comput. Archit. Lett.
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2019 J jnl
A Machine Learning Accelerator In-Memory for Energy Harvesting.
CoRR
Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2019 — ch.
Approximate Ultra-Low Voltage Many-Core Processor Design.
Approximate Circuits
Nam Sung Kim, Ulya R. Karpuzcu
2019 — conf
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.
IISWC
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2019 J jnl
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation.
IEEE Trans. Very Large Scale Integr. Syst.
Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse
2019 J jnl
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping.
IEEE Trans. Computers
Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2019 A* conf
POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities.
HPCA
S. Karen Khatamifard, Longfei Wang, Amitabh Das, Selçuk Köse, Ulya R. Karpuzcu
2019 Misc conf
Special Session: Does Approximation Make Testing Harder (or Easier)?
VTS
R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic
2019 — conf
True In-memory Computing with the CRAM: From Technology to Applications.
ACM Great Lakes Symposium on VLSI
Masoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2019 — conf
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform.
ISQED
Masoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2018 J jnl
A New Class of Covert Channels Exploiting Power Management Vulnerabilities.
IEEE Comput. Archit. Lett.
S. Karen Khatamifard, Longfei Wang, Selçuk Köse, Ulya R. Karpuzcu
2018 J jnl
AISC: Approximate Instruction Set Computer.
CoRR
Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu
2018 J jnl
Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems.
ACM Comput. Surv.
Filipe Betzel, S. Karen Khatamifard, Harini Suresh, David J. Lilja, John Sartori, Ulya R. Karpuzcu
2018 J jnl
Computational RAM to Accelerate String Matching at Scale.
CoRR
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhengyang Zhao, Masoud Zabihi, Salonik Resch, Meisam Razaviyayn, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2018 J jnl
Efficient In-Memory Processing Using Spintronics.
IEEE Comput. Archit. Lett.
Zamshed I. Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew Lyle, Sachin S. Sapatnekar, Ulya R. Karpuzcu, Jianping Wang
2018 J jnl
Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators.
CoRR
Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2018 A conf
Mitigation of NBTI induced performance degradation in on-chip digital LDOs.
DATE
Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse
2018 J jnl
On Approximate Speculative Lock Elision.
IEEE Trans. Multi Scale Comput. Syst.
S. Karen Khatamifard, Ismail Akturk, Ulya R. Karpuzcu
2018 J jnl
On Memory System Design for Stochastic Computing.
IEEE Comput. Archit. Lett.
S. Karen Khatamifard, M. Hassan Najafi, Ali Ghoreyshi, Ulya R. Karpuzcu, David J. Lilja
2018 J jnl
Toward Dynamic Precision Scaling.
IEEE Micro
Serif Yesil, Ismail Akturk, Ulya R. Karpuzcu
2017 J jnl
A Non-volatile Near-Memory Read Mapping Accelerator.
CoRR
S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu
2017 A* conf
AMNESIAC: Amnesic Automatic Computer.
ASPLOS
Ismail Akturk, Ulya R. Karpuzcu
2017 J jnl
Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Longfei Wang, S. Karen Khatamifard, Orhun Aras Uzun, Ulya R. Karpuzcu, Selçuk Köse
2017 J jnl
On Dynamic Precision Scaling.
CoRR
Serif Yesil, Ismail Akturk, Ulya R. Karpuzcu
2017 J jnl
On Memory System Design for Stochastic Computing.
CoRR
S. Karen Khatamifard, M. Hassan Najafi, Ali Ghoreyshi, Ulya R. Karpuzcu, David J. Lilja
2017 J jnl
Recomputation Enabled Efficient Checkpointing.
CoRR
Ismail Akturk, Ulya R. Karpuzcu
2017 A* conf
ThermoGater: Thermally-Aware On-Chip Voltage Regulation.
ISCA
S. Karen Khatamifard, Longfei Wang, Weize Yu, Selçuk Köse, Ulya R. Karpuzcu
2017 J jnl
Trading Computation for Communication: A Taxonomy.
CoRR
Ismail Akturk, Ulya R. Karpuzcu
2016 J jnl
Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance.
ACM Trans. Archit. Code Optim.
Ismail Akturk, Riad Akram, Mohammad Majharul Islam, Abdullah Muzahid, Ulya R. Karpuzcu
2016 A* conf
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.
MICRO
Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
2016 J jnl
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim
2016 C conf
VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches.
ICCD
S. Karen Khatamifard, Michael Resch, Nam Sung Kim, Ulya R. Karpuzcu
2015 C conf
Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications.
ICCD
Hamid Reza Ghasemi, Ulya R. Karpuzcu, Nam Sung Kim
2015 J jnl
Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing.
IEEE Micro
Ismail Akturk, Nam Sung Kim, Ulya R. Karpuzcu
2014 A* conf
Accordion: Toward soft Near-Threshold Voltage Computing.
HPCA
Ulya R. Karpuzcu, Ismail Akturk, Nam Sung Kim
2014 J jnl
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Abhishek A. Sinkar, Hamid Reza Ghasemi, Michael J. Schulte, Ulya R. Karpuzcu, Nam Sung Kim
2013 J jnl
Coping with Parametric Variation at Near-Threshold Voltages.
IEEE Micro
Ulya R. Karpuzcu, Nam Sung Kim, Josep Torrellas
2013 A* conf
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing.
HPCA
Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas
2012 — —
Novel many-core architectures for energy-efficiency
Ulya R. Karpuzcu
2012 A conf
VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages.
DSN
Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim, Josep Torrellas
2010 A* conf
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores.
HPCA
Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas
2009 A* conf
Accurate microarchitecture-level fault modeling for studying hardware faults.
HPCA
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve
2009 A* conf
Blueshift: Designing processors for timing speculation from the ground up.
HPCA
Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles
2009 A* conf
The BubbleWrap many-core: popping cores for sequential acceleration.
MICRO
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
2005 — conf
Automatic verilog code generation through grammatical evolution.
GECCO Workshops
Ulya R. Karpuzcu