Ulrich Ramacher

34 papers A* 1A 2C 6Journal 13Unranked 12

Year	Rank	Type	Title / Venue / Authors
2011	C	`conf`	Architecture and implementation of a Software-Defined Radio baseband processor. ISCAS Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington
2007	C	`conf`	Challenges and prospects of SDR for mobile phones. ICCD Ulrich Ramacher
2007	J	`jnl`	Roundtable: Envisioning the Future for Multiprocessor SoC. IEEE Des. Test Comput. Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf
2007	J	`jnl`	Software-Defined Radio Prospects for Multistandard Mobile Phones. Computer Ulrich Ramacher
2005	J	`jnl`	3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
2005	A	`conf`	Automatic speech recognition with neural spike trains. INTERSPEECH Marcus Holmberg, David Gelbart, Ulrich Ramacher, Werner Hemmert
2005	—	`conf`	Embedded vision platform for video surveillance systems. Electronic Imaging: Image and Video Communications and Processing Axel Techmer, Hans-Martin Blüthgen, Cyprian Grassmann, J. A. Ulrich Hachmann, Wolfgang Raab, Ulrich Ramacher
2005	J	`jnl`	Image Segmentation by Networks of Spiking Neurons. Neural Comput. Joachim M. Buhmann, Tilman Lange, Ulrich Ramacher
2005	—	`conf`	Temporal Sound Processing by Cochlear Nucleus Octopus Neurons. ICANN (1) Werner Hemmert, Marcus Holmberg, Ulrich Ramacher
2005	A*	`conf`	Wireless platforms: GOPS for cents and MilliWatts. DAC Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt
2004	—	`conf`	A low-power memory hierarchy for a fully programmable baseband processor. WMPI Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher
2004	—	`conf`	Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
2004	—	`conf`	Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
2003	J	`jnl`	100 GOPS vision processor for automotive applications. SIGARCH Comput. Archit. News Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer
2003	J	`jnl`	A 100-GOPS Programmable Processor for Vehicle Vision Systems. IEEE Des. Test Comput. Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer
2003	—	`conf`	A programmable platform for software-defined radio. SoC Hans-Martin Blüthgen, Cyprian Grassmann, Wolfgang Raab, Ulrich Ramacher
2003	—	`conf`	Correlation-based feature detection using pulsed neural networks. NNSP Arne Heittmann, Ulrich Ramacher
2002	C	`conf`	An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny
2002	—	`conf`	Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. NNSP Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, D. Matolini, René Schüffny
2002	C	`conf`	Application Specific Embedded Processors for Next Generation Communication Systems. ICCD Ulrich Ramacher
2001	A	`conf`	Crosstalk noise in future digital CMOS circuits. DATE Chr. Werner, Ralf Goettsche, A. Wörner, Ulrich Ramacher
1999	—	`conf`	Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik. PEARL Ulrich Ramacher, Wolfgang Raab, Wolfgang Kabatzke
1996	C	`conf`	SEE-1 - A Vision System for Use in Real World Environments. ICANN Ulrich Ramacher
1995	—	`conf`	SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. IPPS Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer
1993	J	`jnl`	A general-purpose signal processor architecture for neurocomputing and preprocessing applications. J. VLSI Signal Process. Ulrich Ramacher, Jörg Beichter, Nico Brüls
1993	C	`conf`	Architecture and VLSI Design of a VLSI Neural Signal Processor. ISCAS Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder
1993	J	`jnl`	Design of a general-purpose neural signal processor. Neurocomputing Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar
1993	J	`jnl`	Hamiltonian dynamics of neural networks. Neural Networks Ulrich Ramacher
1993	J	`jnl`	Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. Int. J. Neural Syst. Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz
1993	J	`jnl`	Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips. Int. J. Neural Syst. Ulrich Ramacher, Peter Schildberg
1992	J	`jnl`	Mikroelektronische Realisierung von künstlichen neuronalen Netzen / Microelectronic Realizations of artificial neural networks. it Inf. Technol. Karl Goser, Ulrich Ramacher
1992	J	`jnl`	SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine. J. Parallel Distributed Comput. Ulrich Ramacher
1990	—	`conf`	Fine-grain system architectures for systolic emulation of neural algorithms. ASAP Ulrich Ramacher, Wolfgang Raab
1989	—	`conf`	Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area. Fehlertolerierende Rechensysteme Matthias Wesseling, Ulrich Ramacher, Karl Goser