Ulrich Nageldinger

25 papers A 2B 7C 3Unranked 12
YearRankTypeTitle / Venue / Authors
2008 C conf
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited).
FDL
Jochen Zimmermann, Oliver Bringmann, Joachim Gerlach, Florian Schaefer, Ulrich Nageldinger
2008 C conf
Generating MARTE Allocation Models from Activity Threads.
FDL
Andreas W. Liehr, Heike S. Rolfs, Klaus Buchenrieder, Ulrich Nageldinger
2008 — conf
Generation of MARTE Allocation Models from Activity Threads.
FDL (Selected Papers)
Andreas W. Liehr, Klaus J. Buchenrieder, Heike S. Rolfs, Ulrich Nageldinger
2005 A conf
A Low-Cost Realization of an Adaptable Protocol Processing Unit.
IPDPS
Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger
2005 — conf
Reducing the Power Consumption of FPGAs through Retiming.
ECBS
Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger
2002 B conf
Integration of Reconfigurable Hardware into System-Level Design.
FPL
Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier
2002 C conf
System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model.
IEEE International Workshop on Rapid System Prototyping
Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier
2001 — book
Coarse-grained reconfigurable architecture design space exploration.
Ulrich Nageldinger
2000 — conf
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.
PATMOS
Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
2000 B conf
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.
FPL
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
2000 — conf
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array.
ASP-DAC
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
2000 A conf
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract).
FPGA
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1999 B conf
An Internet Based Development Framework for Reconfigurable Computing.
FPL
Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
1999 — conf
Interfacing the MoM-PDA to an Internet-based Development System.
HICSS
Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
1999 B conf
Mapping Applications onto Reconfigurable Kress Arrays.
FPL
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1999 — conf
XMDS: The Xputer Multimedia Development System.
HICSS
Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
1998 B conf
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators.
FPL
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998 — conf
On Reconfigurable Co-processing Units.
IPPS/SPDP Workshops
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998 — conf
Parallelization in Co-Compilation for Configurable Accelerators.
ASP-DAC
Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
1997 — conf
A Novel Sequencer Hardware for Application Specific Computing.
ASAP
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997 — conf
A Novel Universal Sequencer Hardware.
ARCS
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997 B conf
An operating system for custom computing machines based on the Xputer paradigm.
FPL
Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
1997 B conf
Data scheduling to increase performance of parallel accelerators.
FPL
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1996 — conf
A Partitioning Programming Environment for a Novel Parallel Architecture.
IPPS
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996 — conf
A Synthesis System For Bus-Based Wavefront Array Architectures.
ASAP
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger