Ulrich Kühne - RankMe

57 papers A* 1A 4B 4C 10Journal 8Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Execution Platform Contracts. DSD Dorian Bourgeoisat, Ulrich Kühne, Florian Brandner
2025	—	`conf`	Robust and Reliable PUF Protocol Exploiting Non-monotonic Quantization and Neyman-Pearson Lemma. CASCADE Neelam Nasir, Julien Béguinot, Wei Cheng, Ulrich Kühne, Jean-Luc Danger
2022	J	`jnl`	Finding Optimal Moving Target Defense Strategies: A Resilience Booster for Connected Cars. Inf. Maxime Ayrault, Ulrich Kühne, Etienne Borde
2021	—	`conf`	Analysis and Protection of the Two-Metric Helper Data Scheme. COSADE Lars Tebelmann, Ulrich Kühne, Jean-Luc Danger, Michael Pehl
2021	J	`jnl`	Analysis and Protection of the Two-metric Helper Data Scheme. IACR Cryptol. ePrint Arch. Lars Tebelmann, Ulrich Kühne, Jean-Luc Danger, Michael Pehl
2021	C	`conf`	Moving Target Defense Strategy in Critical Embedded Systems: A Game-theoretic Approach. PRDC Maxime Ayrault, Etienne Borde, Ulrich Kühne, Jean Leneutre
2021	—	`conf`	Parasite: Mitigating Physical Side-Channel Attacks Against Neural Networks. SPACE Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
2021	J	`jnl`	Side channel attacks for architecture extraction of neural networks. CAAI Trans. Intell. Technol. Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
2021	—	`conf`	Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks. ACNS (1) Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
2020	—	`conf`	Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks. COSADE Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert, Baptiste Pecatte
2019	C	`conf`	LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection. DSD Jean-Luc Danger, Laurent Fribourg, Ulrich Kühne, Maha Naceur
2019	—	`ed.`	Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, PROOFS 2019, colocated with CHES 2018, Atlanta, GA, USA, August 24, 2019 PROOFS Karine Heydemann, Ulrich Kühne, Letitia Li
2019	—	`conf`	Run or Hide? Both! A Method Based on IPv6 Address Switching to Escape While Being Hidden. MTD@CCS Maxime Ayrault, Etienne Borde, Ulrich Kühne
2018	J	`jnl`	Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
2018	C	`conf`	CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity. DSD Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert
2018	—	`ed.`	PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018 PROOFS Lejla Batina, Ulrich Kühne, Nele Mentens
2017	—	`ed.`	PROOFS 2017, 6th International Workshop on Security Proofs for Embedded Systems, Taipei, Taiwan, September 29th, 2017 PROOFS Ulrich Kühne, Jean-Luc Danger, Sylvain Guilley
2016	A	`conf`	Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2015	A*	`conf`	A generic representation of CCSL time constraints for UML/MARTE models. DAC Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
2015	C	`conf`	Ensuring safety and reliability of IP-based system design - A container approach. RSP Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
2015	—	`ed.`	Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 SyDe Summer School Rolf Drechsler, Ulrich Kühne
2015	—	`conf`	Game-based Synthesis of Distributed Controllers for Sampled Switched Systems. SynCoP Laurent Fribourg, Ulrich Kühne, Nicolas Markey
2015	—	`conf`	Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
2014	C	`conf`	Automatic refinement checking for formal system models. FDL Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
2014	—	`conf`	Behaviour Driven Development for Tests and Verification. TAP@STAF Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2014	J	`jnl`	Finite controlled invariants for sampled switched systems. Formal Methods Syst. Des. Laurent Fribourg, Ulrich Kühne, Romain Soulat
2014	—	`conf`	Safe IP Integration Using Container Modules. ISED Rolf Drechsler, Ulrich Kühne
2014	B	`conf`	Verification of the decimal floating-point square root operation. ETS Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne
2014	C	`conf`	Verifying consistency between activity diagrams and their corresponding OCL contracts. FDL Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
2013	—	`conf`	Constructing Attractors of Nonlinear Dynamical Systems. FSFMA Laurent Fribourg, Ulrich Kühne, Romain Soulat
2013	J	`jnl`	Parametric Verification and Test Coverage for Hybrid Automata using the inverse Method. Int. J. Found. Comput. Sci. Laurent Fribourg, Ulrich Kühne
2012	B	`conf`	Completeness-Driven Development. ICGT Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille
2012	B	`conf`	IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems. FM Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
2011	C	`conf`	Automatic property generation for the formal verification of bus bridges. DDECS Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method. RP Laurent Fribourg, Ulrich Kühne
2011	—	`conf`	Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	—	`conf`	Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	—	`conf`	Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
2010	B	`conf`	Automated formal verification of processors based on architectural models. FMCAD Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow
2010	J	`jnl`	Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. Ulrich Kühne, Daniel Große, Rolf Drechsler
2009	—	`—`	Advanced automation in formal verification of processors. Ulrich Kühne
2009	—	`conf`	Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2009	C	`conf`	Generating an Efficient Instruction Set Simulator from a Complete Property Suite. IEEE International Workshop on Rapid System Prototyping Ulrich Kühne, Sven Beyer, Christian Pichler
2009	—	`conf`	Increasing the Accuracy of SAT-based Debugging. MBMV André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Increasing the accuracy of SAT-based debugging. DATE André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Property analysis and design understanding. DATE Ulrich Kühne, Daniel Große, Rolf Drechsler
2009	C	`conf`	WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2008	J	`jnl`	Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Ulrich Kühne, Rolf Drechsler
2008	—	`conf`	Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV Ulrich Kühne, Daniel Große, Rolf Drechsler
2008	—	`conf`	Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2007	A	`conf`	Estimating functional coverage in bounded model checking. DATE Daniel Große, Ulrich Kühne, Rolf Drechsler
2007	—	`conf`	Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI Ulrich Kühne, Daniel Große, Rolf Drechsler
2006	—	`conf`	Finding Compact BDDs Using Genetic Programming. EvoWorkshops Ulrich Kühne, Nicole Drechsler
2006	—	`conf`	HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	—	`conf`	Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	—	`conf`	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV Daniel Große, Ulrich Kühne, Rolf Drechsler