Ulf Schlichtmann

446 papers A* 35A 101B 10C 22Misc 5Journal 155Unranked 114
YearRankTypeTitle / Venue / Authors
2026 — conf
Accessible Ratio-Specific Mixing: Single-Pressure-Driven Multi-Reagent Mixer Design and Synthesis for 3D-Printed Microfluidics.
ASP-DAC
Yushen Zhang, Debraj Kundu, Tsun-Ming Tseng, Sudip Roy, Shigeru Yamashita, Ulf Schlichtmann
2026 — conf
Built-In Self-Test for Locating Leakage Defects on Continuous-Flow Microfluidic Chips.
ASP-DAC
Jiahui Peng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2026 J jnl
HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst.
Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2026 — conf
Invited: Navigating the Frontier of Optimality and Complexity: Advanced Design Automation for Wavelength-Routed ONoCs.
ISPD
Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2026 J jnl
OptINC: Optical In-Network-Computing for Scalable Distributed Learning.
CoRR
Sijie Fei, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2026 J jnl
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Lian, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2026 J jnl
Path-Driven Washing and Drying Co-Optimization in Continuous-Flow Lab-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xing Huang, Jiaxuan Wang, Zhiwen Yu, Bin Guo, Hanbin Ma, Tsung-Yi Ho, Ulf Schlichtmann, Krishnendu Chakrabarty
2026 A* conf
PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer.
AAAI
Ruogu Ding, Xin Ning, Ulf Schlichtmann, Weikang Qian
2026 — conf
Quantifying Compiler-induced Reliability Loss in Software-Implemented Hardware Fault Tolerance.
ASP-DAC
Davide Baroffio, Johannes Geier, Federico Reghenzani, Ulf Schlichtmann, William Fornaciari
2025 — conf
3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control.
ASP-DAC
Yushen Zhang, Dragan Raseta, Tsun-Ming Tseng, Ulf Schlichtmann
2025 — conf
A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies.
ASP-DAC
Zhidan Zheng, You-Jen Chang, Liaoyuan Cheng, Tsun-Ming Tseng, Ulf Schlichtmann
2025 J jnl
A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization.
CoRR
Samira Ahmadifarsani, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 J jnl
A Homogeneous FeFET-Based Time-Domain Compute-in-Memory Fabric for Matrix-Vector Multiplication and Associative Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xunzhao Yin, Qingrong Huang, Hamza Errahmouni Barkam, Franz Müller, Shan Deng, Alptekin Vardar, Sourav De, Zhouhang Jiang, Mohsen Imani, Ulf Schlichtmann, Xiaobo Sharon Hu, Cheng Zhuo, Thomas Kämpfe, Kai Ni
2025 — conf
A Lifetime Extension Framework for Communication-Intensive Systems Based on Wavelength-Routed Optical Networks-on-Chip.
ACM Great Lakes Symposium on VLSI
Zhidan Zheng, Liaoyuan Cheng, Jeng-De Chang, Tsun-Ming Tseng, Ing-Chao Lin, Ulf Schlichtmann
2025 J jnl
A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiahao Cai, Hamza Errahmouni Barkam, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2025 — conf
Accurate Fault Detection for Wavelength-Routed Optical Networks-on-Chip Under Thermal Variation.
ACM Great Lakes Symposium on VLSI
Yu Zhou, Zhidan Zheng, Liaoyuan Cheng, Jiahong Huang, Tsun-Ming Tseng, Ulf Schlichtmann
2025 — conf
An Efficient General-Purpose Optical Accelerator for Neural Networks.
ASP-DAC
Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025 A* conf
AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips.
DAC
Siyuan Liang, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2025 B conf
Automated Graph-level Passes for TinyML Fault Tolerance.
IJCNN
Johannes Kappes, Johannes Geier, Phillipp van Kempen, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 J jnl
COSMO: COmpressed Sensing for Models and Logging Optimization in MCU Performance Screening.
IEEE Trans. Computers
Nicolò Bellarmino, Riccardo Cantoro, Sophie M. Fosson, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2025 — conf
CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip.
ASP-DAC
Yan-Ting Chen, Zhidan Zheng, Shao-Yun Fang, Tsun-Ming Tseng, Ulf Schlichtmann
2025 J jnl
Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer: Design, Synthesis, and Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2025 A conf
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design.
DATE
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2025 J jnl
CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference.
CoRR
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2025 J jnl
Deep Learning Strategies for Labeling and Accuracy Optimization in Microcontroller Performance Screening.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2025 — conf
Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips.
ASP-DAC
Meng Lian, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2025 J jnl
Efficient Model Switching in RRAM-Based DNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fang-Yi Gu, Ing-Chao Lin, Bing Li, Ulf Schlichtmann, Grace Li Zhang
2025 C conf
Enabling Machine Learning for Power Modeling via Artificial Netlist Generation.
ISCAS
Philipp Fengler, Junpeng Chen, Sani R. Nassif, Ulf Schlichtmann
2025 A conf
FAB: Fast and Demand-Aware Bandwidth Allocation Method for Wavelength-Routed Optical Networks-on-Chip.
ICCAD
Liaoyuan Cheng, Mengchu Li, Zhidan Zheng, Tsun-Ming Tseng, Ulf Schlichtmann
2025 — conf
FLAR-SVD: Fast and Latency-Aware Singular Value Decomposition for Model Compression.
CVPR Workshops
Moritz Thoma, Jorge Villasante, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Maximilian Groetzinger, Daniil Dylkin, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 A* conf
FT-MUX: A Fault-Tolerant Microfluidic Multiplexer Design.
DAC
Mengchu Li, Jiahui Peng, Tsun-Ming Tseng, Ulf Schlichtmann
2025 — conf
GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification.
MLCAD
Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille
2025 J jnl
GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification.
CoRR
Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille
2025 A conf
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis.
ICCAD
Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025 J jnl
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis.
CoRR
Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025 J jnl
Hybrid Convolution and Vision Transformer NAS Search Space for TinyML Image Classification.
CoRR
Mikhael Djajapermana, Moritz Reiber, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 — conf
HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner.
ASP-DAC
Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang
2025 A* conf
LA-MTL: Latency-Aware Automated Multi-Task Learning.
DAC
Shambhavi Balamuthu Sampath, Sami Sawani, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Claudio Passerone, Walter Stechele
2025 — conf
Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper.
SOCC
Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025 J jnl
Large Language Models (LLMs) for Electronic Design Automation (EDA).
CoRR
Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025 B conf
Large Language Models (LLMs) for Verification, Testing, and Design.
ETS
Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler
2025 A conf
Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device.
DATE
Debraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita, Ulf Schlichtmann
2025 J jnl
Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Lian, Hu Peng, Mengchu Li, Yushen Zhang, Tsun-Ming Tseng, Bernhard Wolfrum, Ulf Schlichtmann
2025 A conf
Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN.
DATE
Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack
2025 A conf
Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage).
DATE
Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn
2025 — conf
Obstacle-Aware Synthesis of the Bus Topology Considering Wire Length Minimization.
ISQED
Meng Lian, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Shejun Sun, Ulf Schlichtmann
2025 — conf
Paradigm-Based Automatic HDL Code Generation Using LLMs.
ISQED
Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2025 J jnl
Paradigm-Based Automatic HDL Code Generation Using LLMs.
CoRR
Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2025 J jnl
PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer.
CoRR
Ruogu Ding, Xin Ning, Ulf Schlichtmann, Weikang Qian
2025 A* conf
Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip.
DAC
Liaoyuan Cheng, Mengchu Li, Tsun-Ming Tseng, Martin Schottenloher, Ulf Schlichtmann
2025 A conf
Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks.
DATE
Johannes Geier, Leonidas Kontopoulos, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 — conf
RepFC: Universal Structural Reparametrization Block for High Performance, Lightweight Deep Neural Networks.
CVPR Workshops
Shambhavi Balamuthu Sampath, Judeson Anthony Fernando, Moritz Thoma, Nael Fasfous, Lukas Frickenstein, Pierpaolo Morì, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Walter Stechele
2025 A conf
SRing: A Sub-Ring Construction Method for Application-Specific Wavelength-Routed Optical NoCs.
DATE
Zhidan Zheng, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2025 Misc conf
Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source.
CODES+ISSS
Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2025 — conf
Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory.
DFT
Chandan Kumar Jha, Sumit Kumar Jha, Ulf Schlichtmann, Rolf Drechsler
2025 A* conf
SuperFast: Fast Supernet Training Using Initial Knowledge.
DAC
Moritz Thoma, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Nael Fasfous, Alexander Frickenstein, Manoj Rohit Vemparala, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 — conf
Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation.
CVPR Workshops
Moritz Thoma, Tobias Preintner, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2025 — conf
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning.
SOCC
Zhuorui Zhao, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025 J jnl
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning.
CoRR
Zhuorui Zhao, Bing Li, Grace Li Zhang, Ulf Schlichtmann
2025 — conf
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency.
ISQED
Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025 J jnl
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency.
CoRR
Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2025 A conf
WROXIM: A Network-Level Simulation Platform for Wavelength-Routed Optical Networks-on-Chip.
ICCAD
Jeng-De Chang, Zhidan Zheng, Liaoyuan Cheng, Liu-Xuan-Wei Zhang, Tsun-Ming Tseng, Ing-Chao Lin, Ulf Schlichtmann
2025 J jnl
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Shaown Mojumder, Simon Friedrich, Emil Matús, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Markus Kock, Gregor Schewior, Darius Grantz, Jens Benndorf, Julian Höfer, Patrick Schmidt, Jürgen Becker, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Yun-Jin Li, Gerhard P. Fettweis
2025 A* conf
iG-kway: Incremental k-way Graph Partitioning on GPU.
DAC
Wan-Luan Lee, Shui Jiang, Dian-Lun Lin, Che Chang, Boyang Zhang, Yi-Hua Chung, Ulf Schlichtmann, Tsung-Yi Ho, Tsung-Wei Huang
2024 J jnl
A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow Acceleration.
IEEE Trans. Parallel Distributed Syst.
Bowen Zhang, Huaxi Gu, Grace Li Zhang, Yintang Yang, Ziteng Ma, Ulf Schlichtmann
2024 A conf
A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation.
DATE
Qingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas Kämpfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo, Xunzhao Yin
2024 J jnl
A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fang-Yi Gu, Cheng-Han Yang, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu, Ulf Schlichtmann
2024 J jnl
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Guang Chen, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann
2024 J jnl
An Efficient General-Purpose Optical Accelerator for Neural Networks.
CoRR
Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2024 — conf
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design.
MLCAD
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024 J jnl
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design.
CoRR
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024 — conf
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models.
MLCAD
Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024 J jnl
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models.
CoRR
Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024 A conf
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks.
ICCAD
Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li
2024 J jnl
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks.
CoRR
Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li
2024 J jnl
Classification-Based Automatic HDL Code Generation Using LLMs.
CoRR
Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2024 A conf
Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks.
DATE
Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024 J jnl
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xing Huang, Huayang Cai, Wenzhong Guo, Genggeng Liu, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann
2024 J jnl
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design.
CoRR
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024 J jnl
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2024 — conf
Embedded Feature Selection in MCU Performance Screening.
DTTIS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2024 J jnl
EncodingNet: A Novel Encoding-Based MAC Design for Efficient Neural Network Acceleration.
IEEE Trans. Circuits Syst. Artif. Intell.
Bo Liu, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
2024 J jnl
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration.
CoRR
Bo Liu, Grace Li Zhang, Xunzhao Yin, Ulf Schlichtmann, Bing Li
2024 J jnl
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Conrad Foik, Robert Kunzelmann, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2024 J jnl
GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers.
IEEE Trans. Biomed. Circuits Syst.
Weiqing Ji, Xingzhuo Guo, Shouan Pan, Fei Long, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
2024 J jnl
LLM-Aided Efficient Hardware Design Automation.
CoRR
Kangwei Xu, Ruidi Qiu, Zhuorui Zhao, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2024 A* conf
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design.
DAC
Siyuan Liang, Yushen Zhang, Rana Altay, Hudson Gasvoda, Mengchu Li, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2024 A* conf
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI).
DAC
Mengchu Li, Hanchen Gu, Yushen Zhang, Siyuan Liang, Hudson Gasvoda, Rana Altay, Ismail Emre Araci, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann
2024 J jnl
LiveMind: Low-latency Large Language Models with Simultaneous Inference.
CoRR
Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024 B conf
Logic Design of Neural Networks for High-Throughput and Low-Power Applications.
ASPDAC
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2024 J jnl
Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference.
CoRR
Christopher Wolters, Xiaoxuan Yang, Ulf Schlichtmann, Toyotaro Suzumura
2024 A conf
Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation.
ICCAD
Liaoyuan Cheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2024 — conf
MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems.
COINS
Alexander Hoffman, Ala Fnayou, Fedor Smirnov, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2024 — conf
MuNAS: TinyML Network Architecture Search Using Goal Attainment and Reinforcement Learning.
MECO
Alexander Hoffman, Ulf Schlichtmann, Daniel Mueller-Gritschneder
2024 A* conf
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip.
DAC
Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann
2024 J jnl
On the Relation Between Reliability and Entropy in Physical Unclonable Functions.
IEEE Des. Test
Vasilii Kulagin, Sergio Vinagrero Gutierrez, Tobias Kilian, Daniel Tille, Ulf Schlichtmann, Giorgio Di Natale, Elena-Ioana Vatajelu
2024 A conf
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation.
DATE
Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2024 A conf
PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems.
DATE
Xing Huang, Jiaxuan Wang, Zhiwen Yu, Bin Guo, Tsung-Yi Ho, Ulf Schlichtmann, Krishnendu Chakrabarty
2024 A conf
RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics.
ICCAD
Siyuan Liang, Rongliang Fu, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2024 A conf
ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates.
DATE
Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann
2024 C conf
Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization.
DSD
Philipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2024 — conf
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes.
ISQED
Philipp Fengler, Sani R. Nassif, Ulf Schlichtmann
2024 — conf
ZuSE-KI-Mobil AI Chip Design Platform: An Overview.
NorCAS
Shaown Mojumder, Simon Friedrich, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Julian Höfer, Patrick Schmidt, Jürgen Becker, Darius Grantz, Markus Kock, Jens Benndorf, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Kay Bierzynski
2024 — conf
muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension.
CF (Companion)
Philipp van Kempen, Jefferson Parker Jones, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2023 J jnl
A Multilabel Active Learning Framework for Microcontroller Performance Screening.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero
2023 A conf
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.
ICCAD
Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2023 A conf
ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation.
ICCAD
Siyuan Liang, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2023 — conf
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.
DFT
Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann
2023 — conf
Area-Efficient Neural Network CD Equalizer for 4×200Gb/s PAM4 CWDM4 Systems.
OFC
Bo Liu, Christian Blümm, Stefano Calabrò, Bing Li, Ulf Schlichtmann
2023 J jnl
BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Di Gao, Zeyu Yang, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2023 — conf
Biologically Plausible Learning on Neuromorphic Hardware Architectures.
MWSCAS
Christopher Wolters, Brady Taylor, Edward Hanson, Xiaoxuan Yang, Ulf Schlichtmann, Yiran Chen
2023 A conf
Class-based Quantization for Neural Networks.
DATE
Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann
2023 — conf
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V.
ASP-DAC
Johannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann
2023 A conf
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.
DATE
Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2023 J jnl
Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Lu Wang, Qingshan Li, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann
2023 A conf
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications.
DATE
Uzair Sharif, Daniel Mueller-Gritschneder, Rafael Stahl, Ulf Schlichtmann
2023 — conf
Enabling Inter-Product Transfer Learning on MCU Performance Screening.
ATS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2023 J jnl
Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks.
CoRR
Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2023 A conf
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems.
DATE
Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann
2023 — conf
FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines.
ISPD
Meng Lian, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2023 — conf
Feature Selection for Cost Reduction In MCU Performance Screening.
LATS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2023 J jnl
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xunzhao Yin, Yu Qian, Mohsen Imani, Kai Ni, Chao Li, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2023 J jnl
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference.
CoRR
Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2023 — conf
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates.
ACM Great Lakes Symposium on VLSI
Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
2023 J jnl
Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA.
IEEE Des. Test
Ulf Schlichtmann, Bing Li, Bei Yu, Raviv Gal
2023 — conf
Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing.
OFC
Amro Eldebiky, Georg Böcherer, Maximilian Schädler, Stefano Calabrò, Bing Li, Ulf Schlichtmann
2023 J jnl
Integrated Test Module Design for Microfluidic Large-Scale Integration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mengchu Li, Yushen Zhang, Ju Young Lee, Hudson Gasvoda, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann
2023 J jnl
Logic Design of Neural Networks for High-Throughput and Low-Power Applications.
CoRR
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann, Bing Li
2023 — conf
MLonMCU: TinyML Benchmarking with Fast Retargeting.
CODAI
Philipp van Kempen, Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2023 J jnl
MLonMCU: TinyML Benchmarking with Fast Retargeting.
CoRR
Philipp van Kempen, Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2023 J jnl
Machine Learning in Advanced IC Design: A Methodological Survey.
IEEE Des. Test
Tinghuan Chen, Grace Li Zhang, Bei Yu, Bing Li, Ulf Schlichtmann
2023 B conf
Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs.
ECRTS
Ahsan Saeed, Denis Hoornaert, Dakshina Dasari, Dirk Ziegenbein, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Andreas Gerstlauer, Renato Mancuso
2023 — conf
MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems.
PARMA-DITAM
Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann
2023 A conf
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network.
ICCAD
Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin
2023 J jnl
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation.
CoRR
Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li
2023 J jnl
Performance Screening Using Functional Path Ring Oscillators.
IEEE Trans. Very Large Scale Integr. Syst.
Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann
2023 A* conf
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.
DAC
Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li
2023 J jnl
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.
CoRR
Richard Petri, Grace Li Zhang, Yiran Chen, Ulf Schlichtmann, Bing Li
2023 — conf
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips.
ACM Great Lakes Symposium on VLSI
Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin
2023 B conf
Semi-Supervised Deep Learning for Microcontroller Performance Screening.
ETS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2023 A conf
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement.
DATE
Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann
2023 — conf
Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA.
CODAI
Samira Ahmadifarsani, Rafael Stahl, Philipp van Kempen, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2023 J jnl
Training PPA Models for Embedded Memories on a Low-data Diet.
ACM Trans. Design Autom. Electr. Syst.
Felix Last, Ulf Schlichtmann
2023 A conf
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.
DATE
Bernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, Maurits Ortmanns, Robert Hesselbarth, Matthias Hiller
2023 A conf
XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers.
DATE
Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2022 A conf
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data.
ITC
Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann
2022 C conf
Aging Aware Retraining for Memristor-based Neuromorphic Computing.
ISCAS
Wenwen Ye, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2022 J jnl
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors.
ACM Trans. Archit. Code Optim.
Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, Ulf Schlichtmann
2022 J jnl
Biologically Plausible Learning on Neuromorphic Hardware Architectures.
CoRR
Christopher Wolters, Brady Taylor, Edward Hanson, Xiaoxuan Yang, Ulf Schlichtmann, Yiran Chen
2022 — conf
COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V.
MECO
Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2022 J jnl
Class-based Quantization for Neural Networks.
CoRR
Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li, Ulf Schlichtmann
2022 A conf
CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design.
ICCAD
Siyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2022 J jnl
Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems.
ACM Comput. Surv.
Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Krishnendu Chakrabarty, Ulf Schlichtmann
2022 J jnl
Contamination-Aware Synthesis for Programmable Microfluidic Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao
2022 A conf
Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale Integration.
DATE
Duan Shen, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2022 C conf
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation.
FDL
Conrad Foik, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2022 J jnl
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.
CoRR
Amro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li, Ulf Schlichtmann
2022 J jnl
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiao Moyuan, Tsun-Ming Tseng, Ulf Schlichtmann
2022 — conf
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level.
ASP-DAC
Felix Last, Ceren Yeni, Ulf Schlichtmann
2022 A* conf
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory.
DAC
Jiahao Cai, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2022 J jnl
Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization.
IEEE Trans. Computers
Xing Huang, Wenzhong Guo, Zhisheng Chen, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2022 A* conf
GNN-based concentration prediction for random microfluidic mixers.
DAC
Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao
2022 A conf
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores.
RTAS
Ahsan Saeed, Dakshina Dasari, Dirk Ziegenbein, Varun Rajasekaran, Falk Rehm, Michael Pressler, Arne Hamann, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann
2022 C conf
Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data.
IOLTS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero
2022 J jnl
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xing Huang, Tsung-Yi Ho, Zepeng Li, Genggeng Liu, Lu Wang, Qingshan Li, Wenzhong Guo, Bing Li, Ulf Schlichtmann
2022 J jnl
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann
2022 C conf
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming.
DSD
Grace Li Zhang, Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann
2022 B conf
Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators.
ETS
Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann
2022 J jnl
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement.
CoRR
Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann
2022 B conf
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip.
ETS
Francesco Angione, Davide Appello, Joseph Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, Juan-David Guerrero-Balaguera, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli
2022 J jnl
VirtualSync+: Timing Optimization With Virtual Synchronization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2022 J jnl
VirtualSync+: Timing Optimization with Virtual Synchronization.
CoRR
Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
2021 J jnl
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs.
ACM Trans. Archit. Code Optim.
Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2021 A conf
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators.
ITC
Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann
2021 A conf
An Efficient Programming Framework for Memristor-based Neuromorphic Computing.
DATE
Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann
2021 A* conf
Bayesian Inference Based Robust Computing on Memristor Crossbar.
DAC
Di Gao, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2021 A conf
BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems.
ICCAD
Xing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann
2021 — conf
Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars.
ASP-DAC
Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann
2021 J jnl
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2021 J jnl
DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices.
Int. J. Parallel Program.
Rafael Stahl, Alexander Hoffman, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann
2021 J jnl
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level.
CoRR
Felix Last, Ceren Yeni, Ulf Schlichtmann
2021 A conf
Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory.
DATE
Yu Qian, Zhenhao Fan, Haoran Wang, Chao Li, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin
2021 B conf
Exploiting Active Learning for Microcontroller Performance Prediction.
ETS
Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero
2021 A conf
FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs.
DATE
Xiao Moyuan, Tsun-Ming Tseng, Ulf Schlichtmann
2021 — conf
Feeding Hungry Models Less: Deep Transfer Learning for Embedded Memory PPA Models : Special Session.
MLCAD
Felix Last, Ulf Schlichtmann
2021 A conf
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs.
DATE
Jingyao Zhang, Huaxi Gu, Grace Li Zhang, Bing Li, Ulf Schlichtmann
2021 — conf
Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores.
MLCAD
Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, Arne Hamann, Dirk Ziegenbein, Ulf Schlichtmann, Andreas Gerstlauer
2021 — conf
Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology.
ASP-DAC
Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2021 A conf
Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics.
ICCAD
Tsun-Ming Tseng, Meng Lian, Mengchu Li, Philipp Rinklin, Leroy Grob, Bernhard Wolfrum, Ulf Schlichtmann
2021 A conf
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing.
ICCAD
Shuhang Zhang, Hai Li, Ulf Schlichtmann
2021 J jnl
REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance.
ACM Trans. Embed. Comput. Syst.
Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2021 A conf
Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips.
ICCAD
Fangda Zuo, Mengchu Li, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann
2021 A conf
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training.
ICCAD
Di Gao, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo
2021 J jnl
Report on First and Second ACM/IEEE Workshop on Machine Learning for CAD (MLCAD).
IEEE Des. Test
Marilyn Wolf, Jörg Henkel, Raviv Gal, Ulf Schlichtmann
2021 — conf
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection.
ISQED
Yu-Kai Chuang, Yong Zhong, Yi-Hao Cheng, Bo-Yi Yu, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2021 — conf
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks.
ASP-DAC
Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann
2021 A conf
ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip.
ICCAD
Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann
2020 A conf
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.
DATE
Shuhang Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2020 J jnl
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
2020 A conf
Countering Variations and Thermal Effects for Accurate Optical Neural Networks.
ICCAD
Ying Zhu, Grace Li Zhang, Bing Li, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann
2020 J jnl
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface.
IEEE Embed. Syst. Lett.
Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2020 J jnl
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
2020 — conf
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation.
ASP-DAC
Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2020 — conf
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.
AICAS
Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2020 — ed.
MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, Virtual Event, Iceland, November 16-20, 2020
MLCAD
Ulf Schlichtmann, Raviv Gal, Hussam Amrouch, Hai (Helen) Li
2020 J jnl
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs.
ACM Trans. Design Autom. Electr. Syst.
Yong Hu, Marcel Mettler, Daniel Mueller-Gritschneder, Thomas Wild, Andreas Herkersdorf, Ulf Schlichtmann
2020 A conf
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors.
ITC
Riccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero
2020 J jnl
Machine learning and structural characteristics for reverse engineering.
Integr.
Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
2020 — conf
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips.
ASP-DAC
Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann
2020 J jnl
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2020 A conf
Overview of 2020 CAD Contest at ICCAD.
ICCAD
Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
2020 A conf
PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction.
ICCAD
Alexandre Truppel, Tsun-Ming Tseng, Ulf Schlichtmann
2020 J jnl
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann
2020 — conf
Partial Sharing Neural Networks for Multi-Target Regression on Power and Performance of Embedded Memories.
MLCAD
Felix Last, Ulf Schlichtmann
2020 A conf
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.
ICCAD
Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann
2020 J jnl
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks.
ACM Trans. Design Autom. Electr. Syst.
Felix Last, Max Haeberlein, Ulf Schlichtmann
2020 J jnl
Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks.
CoRR
Felix Last, Max Haeberlein, Ulf Schlichtmann
2020 — conf
Reliable and Robust RRAM-based Neuromorphic Computing.
ACM Great Lakes Symposium on VLSI
Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li, Ulf Schlichtmann
2020 Misc conf
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs.
VLSID
Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2020 A conf
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise.
DATE
Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann
2020 J jnl
Test Generation for Flow-Based Microfluidic Biochips With General Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2020 — conf
Timing Resilience for Efficient and Secure Circuits.
ASP-DAC
Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann
2020 J jnl
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020 J jnl
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR
Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020 A conf
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.
DATE
Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy
2019 — conf
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation.
ISQED
Xu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou
2019 A* conf
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization.
DAC
Michael Schwarz, Raphael Stahl, Daniel Müller-Gritschneder, Ulf Schlichtmann, Dominik Stoffel, Wolfgang Kunz
2019 A conf
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.
DATE
Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann
2019 A conf
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices.
DATE
Yu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann
2019 A conf
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper.
ICCAD
Tsun-Ming Tseng, Mengchu Li, Yushen Zhang, Tsung-Yi Ho, Ulf Schlichtmann
2019 A* conf
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
DAC
Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra
2019 J jnl
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann
2019 J jnl
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports
Krishnendu Chakrabarty, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann
2019 A conf
Fault Localization in Programmable Microfluidic Devices.
DATE
Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann
2019 — conf
Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices.
SAMOS
Rafael Stahl, Zhuoran Zhao, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann
2019 — conf
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs.
NEWCAS
Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2019 — conf
Machine learning and structural characteristics for reverse engineering.
ASP-DAC
Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann
2019 A* conf
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports.
DAC
Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann
2019 A conf
Overview of 2019 CAD Contest at ICCAD.
ICCAD
Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin
2019 — conf
PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
ISPD
Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann
2019 A conf
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage.
DATE
Zhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2019 A conf
SRAM Design Exploration with Integrated Application-Aware Aging Analysis.
DATE
Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif
2019 — conf
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems.
ASP-DAC
Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2019 J jnl
Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann
2019 J jnl
Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
2019 A conf
Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V.
DATE
Tim Fritzmann, Uzair Sharif, Daniel Müller-Gritschneder, Cezar Reinbrecht, Ulf Schlichtmann, Johanna Sepúlveda
2019 A conf
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips.
ICCAD
Mengchu Li, Tsun-Ming Tseng, Yanlu Ma, Tsung-Yi Ho, Ulf Schlichtmann
2019 A conf
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper.
ICCAD
Tsun-Ming Tseng, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, Ulf Schlichtmann
2018 B conf
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis.
ETS
Yasamin Moradi, Krishnendu Chakrabarty, Ulf Schlichtmann
2018 J jnl
Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Dimo Martev, Sven Hampel, Ulf Schlichtmann
2018 C conf
Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation.
FDL
Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2018 C conf
Automatic Design of Microfluidic Devices.
FDL
Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann
2018 J jnl
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann
2018 A* conf
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration.
DAC
Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Amy Mongersun, Ismail Emre Araci, Tsung-Yi Ho, Ulf Schlichtmann
2018 A conf
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs.
ICCAD
Mengchu Li, Tsun-Ming Tseng, Davide Bertozzi, Mahdi Tala, Ulf Schlichtmann
2018 J jnl
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann
2018 A* conf
Design-for-testability for continuous-flow microfluidic biochips.
DAC
Chunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann
2018 A conf
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
DATE
Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann
2018 C conf
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary.
IOLTS
Petra R. Maier, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2018 J jnl
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices.
Microelectron. J.
Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann
2018 C conf
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping.
IOLTS
Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Kluge, Ulf Schlichtmann
2018 J jnl
Fault Injection for Test-Driven Development of Robust SoC Firmware.
ACM Trans. Embed. Comput. Syst.
Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2018 A conf
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis.
DATE
Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
2018 J jnl
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol.
Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2018 J jnl
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs.
ACM Trans. Design Autom. Electr. Syst.
Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2018 A conf
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.
ICCAD
Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann
2018 — conf
On enabling diagnosis for 1-Pin Test fails in an industrial flow.
ASP-DAC
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
2018 A conf
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML.
ICCAD
Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann
2018 A* conf
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.
DAC
Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2018 — conf
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
ICICDT
Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2018 C conf
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.
ISCAS
Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
2018 — conf
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.
ISVLSI
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2018 A conf
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
DATE
Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann
2018 A* conf
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
DAC
Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann
2018 A conf
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search.
ICCAD
Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2017 — conf
20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics.
SMACD
Shushanik Karapetyan, Ulf Schlichtmann
2017 — ed.
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017
SOCC
Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar
2017 — conf
A Method for Phase Noise Analysis of RF Circuits.
ACM Great Lakes Symposium on VLSI
Dimo Martev, Sven Hampel, Ulf Schlichtmann
2017 J jnl
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017 — conf
Application of machine learning methods in post-silicon yield improvement.
SoCC
Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann
2017 A conf
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform.
DATE
Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
2017 A* conf
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling.
DAC
Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017 J jnl
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.
CoRR
Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann
2017 J jnl
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers.
CoRR
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017 J jnl
Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping.
Microprocess. Microsystems
Elisabeth Glocker, Qingqing Chen, Ulf Schlichtmann, Doris Schmitt-Landsiedel
2017 J jnl
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers.
CoRR
Bing Li, Ning Chen, Ulf Schlichtmann
2017 — conf
Frontiers of timing.
SLIP
Ulf Schlichtmann
2017 — conf
Generative adversarial network based scalable on-chip noise sensor placement.
SoCC
Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi
2017 — conf
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
ASP-DAC
Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017 J jnl
ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing.
CoRR
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017 C conf
Methodology for automated phase noise minimization in RF circuit interconnect trees.
ISCAS
Dimo Martev, Sven Hampel, Ulf Schlichtmann
2017 — conf
Model-based framework for networks-on-chip design space exploration.
AISTECS@HiPEAC
Yong Hu, Daniel Müller-Gritschneder, Ulf Schlichtmann
2017 J jnl
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing.
CoRR
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017 J jnl
On Hierarchical Statistical Static Timing Analysis.
CoRR
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
2017 J jnl
On Timing Model Extraction and Hierarchical Statistical Timing Analysis.
CoRR
Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
2017 J jnl
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model.
CoRR
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017 J jnl
Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards.
CoRR
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017 J jnl
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation.
CoRR
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017 J jnl
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst.
Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017 — conf
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs).
DFT
Bing Li, Ulf Schlichtmann
2017 J jnl
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability.
CoRR
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2017 A conf
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening.
ICCAD
Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann
2017 J jnl
Static Timing Model Extraction for Combinational Circuits.
CoRR
Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
2017 J jnl
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements.
CoRR
Bing Li, Ulf Schlichtmann
2017 J jnl
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations.
CoRR
Bing Li, Ning Chen, Ulf Schlichtmann
2017 J jnl
Storage and Caching: Synthesis of Flow-based Microfluidic Biochips.
CoRR
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2017 J jnl
Testing Microfluidic Fully Programmable Valve Arrays (FPVAs).
CoRR
Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2017 A conf
Testing microfluidic Fully Programmable Valve Arrays (FPVAs).
DATE
Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
2017 C conf
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
RSP
Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann
2017 J jnl
Timing Model Extraction for Sequential Circuits Considering Process Variations.
CoRR
Bing Li, Ning Chen, Ulf Schlichtmann
2017 J jnl
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
CoRR
Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2017 A* conf
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
DAC
Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
2016 A* conf
Columba: co-layout synthesis for continuous-flow microfluidic biochips.
DAC
Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2016 A conf
Control-fluidic CoDesign for paper-based digital microfluidic biochips.
ICCAD
Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
2016 J jnl
Dark silicon management: an integrated and coordinated cross-layer approach.
it Inf. Technol.
Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
2016 J jnl
Editorial.
Microelectron. Reliab.
Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou
2016 A* conf
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.
DAC
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016 C conf
Efficient handling of the fault space in functional safety analysis utilizing formal methods.
VLSI-SoC
Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
2016 Misc conf
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing.
CODES+ISSS
Petra R. Maier, Veit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2016 J jnl
FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies.
Microelectron. Reliab.
Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann
2016 A conf
From biochips to quantum circuits: computer-aided design for emerging technologies.
ICCAD
Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler
2016 — conf
Fully synthesized time-to-digital converter for cellular transceivers.
EBCCSP
Dimo Martev, Sven Hampel, Ulf Schlichtmann
2016 — conf
Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs.
ACM Great Lakes Symposium on VLSI
Munish Jassi, Uzair Sharif, Daniel Müller-Gritschneder, Ulf Schlichtmann
2016 J jnl
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Binjie Cheng, Asen Asenov, Ulf Schlichtmann
2016 A* conf
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.
DAC
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2016 — conf
On the measurement of power grid robustness under load uncertainties.
SmartGridComm
Jie Wu, Ulf Schlichtmann, Yiyu Shi
2016 — conf
PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip.
ISPD
Anja von Beuningen, Ulf Schlichtmann
2016 J jnl
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.
ACM J. Emerg. Technol. Comput. Syst.
Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann
2016 A conf
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.
ICCAD
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016 — conf
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
ASP-DAC
Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
2016 J jnl
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann
2016 — conf
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models.
ISIC
Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann
2016 A conf
Sampling-based buffer insertion for post-silicon yield improvement under process variability.
DATE
Grace Li Zhang, Bing Li, Ulf Schlichtmann
2016 A conf
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations.
DATE
Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2016 — conf
Synthesis-based methodology for high-speed multi-modulus divider.
SMACD
Dimo Martev, Sven Hampel, Ulf Schlichtmann
2016 A conf
Where formal verification can help in functional safety analysis.
ICCAD
Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
2015 J jnl
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Martin Barke, Ulf Schlichtmann
2015 J jnl
Application-aware cross-layer reliability analysis and optimization.
it Inf. Technol.
Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Müller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis
2015 — conf
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
INA-OCMC@HiPEAC
Yong Hu, Daniel Müller-Gritschneder, Martha Johanna Sepúlveda, Guy Gogniat, Ulf Schlichtmann
2015 — conf
Beyond GORDIAN and Kraftwerk: EDA Research at TUM.
ISPD
Ulf Schlichtmann
2015 — conf
Emulation of an ASIC power and temperature monitor system for FPGA prototyping.
ReCoSoC
Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel
2015 A* conf
GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs.
DAC
Munish Jassi, Daniel Müller-Gritschneder, Ulf Schlichtmann
2015 J jnl
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2015 — conf
Integrating aging aware timing analysis into a commercial STA tool.
VLSI-DAT
Shushanik Karapetyan, Ulf Schlichtmann
2015 — conf
MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography.
TRUST
Qingqing Chen, Ulrich Rührmair, Spoorthy Narayana, Uzair Sharif, Ulf Schlichtmann
2015 A* conf
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping.
DAC
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2015 C conf
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
SCOPES
Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann
2015 J jnl
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bing Li, Ulf Schlichtmann
2015 J jnl
Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips.
IEEE Des. Test
Tsun-Ming Tseng, Bing Li, Ulf Schlichtmann, Tsung-Yi Ho
2015 A conf
Timing verification for adaptive integrated circuits.
DATE
Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu
2014 J jnl
A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits.
Microelectron. Reliab.
Veit B. Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel, Ulf Schlichtmann
2014 J jnl
An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms.
IEEE Des. Test
Michael Linder, Alfred Eder, Ulf Schlichtmann, Klaus Oberländer
2014 A conf
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
DATE
Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn
2014 J jnl
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2014 J jnl
Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture.
CoRR
Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel
2014 — conf
Fault-tolerant embedded control systems for unreliable hardware.
ISIC
Dip Goswami, Daniel Mueller-Gritschneder, Twan Basten, Ulf Schlichtmann, Samarjit Chakraborty
2014 J jnl
Monitoring of aging in integrated circuits by identifying possible critical paths.
Microelectron. Reliab.
Dominik Lorenz, Martin Barke, Ulf Schlichtmann
2014 A conf
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations.
DATE
André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann
2014 J jnl
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab.
Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
2014 J jnl
Robustness measurement of integrated circuits and its adaptation to aging effects.
Microelectron. Reliab.
Martin Barke, Michael Kärgel, Markus Olbrich, Ulf Schlichtmann
2014 A* conf
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.
DAC
Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
2014 J jnl
Special section reliability and variability of devices for circuits and systems.
Microelectron. Reliab.
Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou
2014 A conf
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks.
DATE
Ulrich Rührmair, Ulf Schlichtmann, Wayne P. Burleson
2014 — conf
System C-based multi-level error injection for the evaluation of fault-tolerant systems.
ISIC
Daniel Mueller-Gritschneder, Petra R. Maier, Marc Greim, Ulf Schlichtmann
2014 A* conf
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience.
DAC
Veit Kleeberger, Petra R. Maier, Ulf Schlichtmann
2013 J jnl
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro
Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn
2013 — conf
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.
NOCS
Amit Verma, Pritpal S. Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann
2013 A conf
A spectral clustering approach to application-specific network-on-chip synthesis.
DATE
Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2013 A conf
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot.
DATE
Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann
2013 A conf
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts.
DATE
Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2013 — conf
Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty.
SysCon
Carsten Uphoff, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2013 A conf
Fast cache simulation for host-compiled simulation of embedded software.
DATE
Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2013 — conf
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.
ASP-DAC
Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2013 J jnl
On Timing Model Extraction and Hierarchical Statistical Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
2013 A conf
PROTON: an automatic place-and-route tool for optical networks-on-chip.
ICCAD
Anja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi
2013 A conf
Post-route alleviation of dense meander segments in high-performance printed circuit boards.
ICCAD
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2013 — conf
Post-route refinement for high-frequency PCBs considering meander segment alleviation.
ACM Great Lakes Symposium on VLSI
Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
2013 A* conf
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies.
DAC
Veit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann
2013 A* conf
Reliability challenges for electric vehicles: from devices to architecture and systems software.
DAC
Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty
2013 — conf
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling.
DFTS
Veit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2012 A conf
Accurately timed transaction level models for virtual prototyping at high abstraction level.
DATE
Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2012 A conf
Automated construction of a cycle-approximate transaction level model of a memory controller.
DATE
Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
2012 A conf
Characterization of the bistable ring PUF.
DATE
Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair
2012 A conf
Current source modeling for power and timing analysis at different supply voltages.
DATE
Christoph Knoth, Hela Jedda, Ulf Schlichtmann
2012 J jnl
Efficiently analyzing the impact of aging effects on large integrated circuits.
Microelectron. Reliab.
Dominik Lorenz, Martin Barke, Ulf Schlichtmann
2012 — conf
Hierarchical control flow matching for source-level simulation of embedded software.
ISSoC
Kun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann
2012 J jnl
ICMAT 2011 - Reliability and variability of semiconductor devices and ICs.
Microelectron. Reliab.
Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou
2012 J jnl
Iterative timing analysis based on nonlinear and interdependent flipflop modelling.
IET Circuits Devices Syst.
Ning Chen, Bing Li, Ulf Schlichtmann
2012 Misc conf
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
CODES+ISSS
Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann
2012 B conf
Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling.
RTCSA
Alejandro Masrur, Philipp H. Kindt, Martin Becker, Samarjit Chakraborty, Veit Kleeberger, Martin Barke, Ulf Schlichtmann
2012 J jnl
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bing Li, Ning Chen, Ulf Schlichtmann
2011 J jnl
Circuit-Based Approaches to Simpl Systems.
J. Circuits Syst. Comput.
Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, Ulrich Rührmair
2011 J jnl
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb
2011 C conf
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
DSD
Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann
2011 Misc conf
Design and architectures for dependable embedded systems.
CODES+ISSS
Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
2011 — conf
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times.
PATMOS
Ning Chen, Bing Li, Ulf Schlichtmann
2011 — conf
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation.
ICSAMOS
Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2011 — conf
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging.
PATMOS
Christoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann
2011 — conf
The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions.
HOST
Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair
2011 — conf
Timing Modeling of Flipflops Considering Aging Effects.
PATMOS
Ning Chen, Bing Li, Ulf Schlichtmann
2010 A conf
Aging analysis at gate and macro cell level.
ICCAD
Dominik Lorenz, Martin Barke, Ulf Schlichtmann
2010 J jnl
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it Inf. Technol.
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
2010 — conf
Automatic generation of hierarchical placement rules for analog integrated circuits.
ISPD
Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann
2010 A conf
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.
ICCAD
Bing Li, Ning Chen, Ulf Schlichtmann
2010 C conf
Towards Electrical, Integrated Implementations of SIMPL Systems.
WISTP
Ulrich Rührmair, Qingqing Chen, Martin Stutzmann, Paolo Lugli, Ulf Schlichtmann, György Csaba
2010 — conf
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation.
PATMOS
Christoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann
2009 J jnl
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.
SIAM J. Optim.
Daniel Mueller-Gritschneder, Helmut E. Graeb, Ulf Schlichtmann
2009 — conf
A free-shape router for analog and RF applications.
ECCTD
Engin Avci, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
2009 C conf
Aging analysis of circuit timing considering NBTI and HCI.
IOLTS
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
2009 A conf
Digital design at a crossroads How to make statistical design methodologies industrially relevant.
DATE
Ulf Schlichtmann, Manuel Schmidt, Harald Kinzelbach, Michael Pronath, Volker Glöckel, Manfred Dietrich, Uwe Eichler, Joachim Haase
2009 — conf
Fast and waveform independent characterization of current source models.
BMAS
Christoph Knoth, Veit B. Kleeberger, Petra Nordholz, Ulf Schlichtmann
2009 A conf
On hierarchical statistical static timing analysis.
DATE
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
2009 J jnl
On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions.
IACR Cryptol. ePrint Arch.
György Csaba, Xueming Ju, Qingqing Chen, Wolfgang Porod, Jürgen Schmidhuber, Ulf Schlichtmann, Paolo Lugli, Ulrich Rührmair
2009 J jnl
Pareto optimization of analog circuits considering variability.
Int. J. Circuit Theory Appl.
Helmut Graeb, Daniel Mueller-Gritschneder, Ulf Schlichtmann
2009 — conf
Sensitivity based parameter reduction for statistical analysis of circuit performance.
ICECS
Ning Chen, Bing Li, Ulf Schlichtmann
2009 A conf
Timing model extraction for sequential circuits considering process variations.
ICCAD
Bing Li, Ning Chen, Ulf Schlichtmann
2009 J jnl
Towards Electrical, Integrated Implementations of SIMPL Systems.
IACR Cryptol. ePrint Arch.
Ulrich Rührmair, Qingqing Chen, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, György Csaba
2008 — conf
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA.
PATMOS
Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
2008 C conf
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.
ICCD
Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2008 — conf
Abacus: fast legalization of standard cell circuits with minimal movement.
ISPD
Peter Spindler, Ulf Schlichtmann, Frank M. Johannes
2008 A conf
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions.
ICCAD
Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes
2008 J jnl
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peter Spindler, Ulf Schlichtmann, Frank M. Johannes
2008 A conf
Sizing Rules for Bipolar Analog Circuit Design.
DATE
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2008 — conf
Static Timing Model Extraction for Combinational Circuits.
PATMOS
Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
2008 J jnl
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2007 — conf
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts.
CICC
Jun Zou, Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
2007 — conf
Pareto optimization of analog circuits considering variability.
ECCTD
Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
2007 — conf
Pareto-Front Computation and Automatic Sizing of CPPLLs.
ISQED
Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2007 A conf
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
DATE
Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2006 A* conf
A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
DAC
Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
2006 A conf
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
DATE
Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp
2006 C conf
Fast evaluation of analog circuit structures by polytopal approximations.
ISCAS
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2005 A* conf
Deterministic approaches to analog performance space exploration (PSE).
DAC
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2005 — conf
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen.
GI Jahrestagung (1)
Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann
2004 C conf
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance.
DSD
Ulf Schlichtmann
2004 A conf
Extremely Low-Power Logic.
DATE
Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann
2004 — ch.
Ultra-Low-Power Design: Device and Logic Design Approaches.
Ultra Low-Power Electronics and Design
Christoph Heer, Ulf Schlichtmann
2002 A conf
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs.
DATE
K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment
2002 C conf
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development.
DSD
Ulf Schlichtmann
2002 — conf
Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today.
ISQED
Ulf Schlichtmann
1999 J jnl
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich
1996 J jnl
Fast Power Estimation of Large Circuits.
IEEE Des. Test Comput.
Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth
1995 — —
Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine.
Ulf Schlichtmann
1994 — conf
A new power estimation technique with application to decomposition of Boolean functions for low power.
EURO-DAC
Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann
1992 A* conf
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping.
DAC
Ulf Schlichtmann, Franc Brglez, Michael Hermann
1991 — conf
Goal oriented slicing enumeration through shape function clipping.
EURO-DAC
Georg Sigl, Ulf Schlichtmann