Uday Bondhugula

58 papers A* 8A 12B 16Misc 2Journal 19Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
PolyBlocks: A Compiler Infrastructure for AI Chips and Programming Frameworks.
CoRR
Uday Bondhugula, Akshay Baviskar, Navdeep Katel, Vimal Patel, Anoop JS, Arnab Dutta
2026 B ed.
Proceedings of the 35th ACM SIGPLAN International Conference on Compiler Construction, CC 2026, Sydney, NSW, Australia, 31 January 2026 - 1 February 2026
CC
Martin Kong, Uday Bondhugula, Tobias Grosser
2024 A* conf
SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference.
SOSP
Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula
2023 J jnl
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators.
CoRR
Kingshuk Majumder, Uday Bondhugula
2023 — conf
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description.
ASPLOS (4)
Kingshuk Majumder, Uday Bondhugula
2022 B conf
MLIR-based code generation for GPU tensor cores.
CC
Navdeep Katel, Vivek Khandelwal, Uday Bondhugula
2022 A* conf
Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference.
MICRO
Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula
2021 A conf
A practical tile size selection model for affine loop nests.
ICS
Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, Uday Bondhugula
2021 J jnl
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description.
CoRR
Kingshuk Majumder, Uday Bondhugula
2021 J jnl
High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results.
CoRR
Navdeep Katel, Vivek Khandelwal, Uday Bondhugula
2021 A conf
MLIR: Scaling Compiler Infrastructure for Domain Specific Computation.
CGO
Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, Oleksandr Zinenko
2020 J jnl
An Effective Fusion and Tile Size Model for PolyMage.
ACM Trans. Program. Lang. Syst.
Abhinav Jangda, Uday Bondhugula
2020 B conf
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers.
CC
Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula
2020 J jnl
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs.
ACM Trans. Archit. Code Optim.
Aravind Acharya, Uday Bondhugula, Albert Cohen
2020 J jnl
High Performance Code Generation in MLIR: An Early Case Study with GEMM.
CoRR
Uday Bondhugula
2020 J jnl
MLIR: A Compiler Infrastructure for the End of Moore's Law.
CoRR
Chris Lattner, Jacques A. Pienaar, Mehdi Amini, Uday Bondhugula, River Riddle, Albert Cohen, Tatiana Shpeisman, Andy Davis, Nicolas Vasilache, Oleksandr Zinenko
2020 J jnl
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems.
ACM Trans. Parallel Comput.
Karan Aggarwal, Uday Bondhugula
2019 J jnl
A flexible FPGA accelerator for convolutional neural networks.
CoRR
Kingshuk Majumder, Uday Bondhugula
2019 J jnl
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems.
CoRR
Karan Aggarwal, Uday Bondhugula, Varsha Sreenivasan, Devarajan Sridharan
2019 A conf
Optimizing the linear fascicle evaluation algorithm for many-core systems.
ICS
Karan Aggarwal, Uday Bondhugula
2018 J jnl
An Approach for Finding Permutations Quickly: Fusion and Dimension matching.
CoRR
Aravind Acharya, Uday Bondhugula, Albert Cohen
2018 B conf
An effective fusion and tile size model for optimizing image processing pipelines.
PPoPP
Abhinav Jangda, Uday Bondhugula
2018 A* conf
Polyhedral auto-transformation with no integer linear programming.
PLDI
Aravind Acharya, Uday Bondhugula, Albert Cohen
2018 J jnl
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths.
CoRR
Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula
2017 J jnl
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations.
IEEE Trans. Parallel Distributed Syst.
Uday Bondhugula, Vinayaka Bandishti, Irshad Pananilath
2017 A conf
Optimizing geometric multigrid method computation using a DSL approach.
SC
Vinay Vasista, Kumudha Narasimhan, Siddharth Bhat, Uday Bondhugula
2016 B conf
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs.
PACT
Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula
2016 J jnl
Automatic Storage Optimization for Arrays.
ACM Trans. Program. Lang. Syst.
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen
2016 J jnl
Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory.
ACM Trans. Parallel Comput.
Roshan Dathathri, Ravi Teja Mullapudi, Uday Bondhugula
2016 A* conf
SMO: an integrated approach to intra-array and inter-array storage optimization.
POPL
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen
2016 J jnl
The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests.
ACM Trans. Program. Lang. Syst.
Uday Bondhugula, Aravind Acharya, Albert Cohen
2015 J jnl
An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations.
ACM Trans. Archit. Code Optim.
Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula
2015 B conf
PLUTO+: near-complete modeling of affine transformations for parallelism and locality.
PPoPP
Aravind Acharya, Uday Bondhugula
2015 A* conf
PolyMage: Automatic Optimization for Image Processing Pipelines.
ASPLOS
Ravi Teja Mullapudi, Vinay Vasista, Uday Bondhugula
2014 A conf
Effective automatic computation placement and dataallocation for parallelization of regular programs.
ICS
Chandan Reddy, Uday Bondhugula
2014 B conf
Tiling and optimizing time-iterated computations on periodic domains.
PACT
Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache
2013 J jnl
Automatic data allocation and buffer management for multi-GPU machines.
ACM Trans. Archit. Code Optim.
Thejas Ramashekar, Uday Bondhugula
2013 A conf
Compiling affine loop nests for distributed-memory parallel architectures.
SC
Uday Bondhugula
2013 B conf
Generating efficient data movement code for heterogeneous architectures with distributed-memory.
PACT
Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula
2013 B conf
PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language.
CC
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula
2012 A conf
Tiling stencil computations to maximize parallelism.
SC
Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula
2011 A* conf
Loop transformations: convexity, pruning and optimization.
POPL
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache
2010 B conf
A model for fusion and code motion in an automatic parallelizing compiler.
PACT
Uday Bondhugula, Oktay Günlük, Sanjeeb Dash, Lakshminarayanan Renganarayanan
2010 B conf
Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application!
PACT
Rajesh Bordawekar, Uday Bondhugula, Ravi Rao
2010 A conf
Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework.
SC
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan
2009 A conf
Compact multi-dimensional kernel extraction for register tiling.
SC
Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien
2009 B conf
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors.
PPoPP
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan
2009 B conf
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors.
PACT
Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai
2008 A conf
A compiler framework for optimization of affine loop nests for gpgpus.
ICS
Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
2008 A* conf
A practical automatic polyhedral parallelizer and locality optimizer.
PLDI
Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan
2008 B conf
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model.
CC
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
2008 B conf
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.
PPoPP
Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
2008 A conf
Towards effective automatic parallelization for multicore systems.
IPDPS
Uday Bondhugula, Muthu Manikandan Baskaran, Albert Hartono, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
2007 B conf
Automatic mapping of nested loops to FPGAS.
PPoPP
Uday Bondhugula, J. Ramanujam, P. Sadayappan
2007 A* conf
Effective automatic parallelization of stencil computations.
PLDI
Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan
2006 Misc conf
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.
FCCM
Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan
2006 A conf
Parallel FPGA-based all-pairs shortest-paths in a directed graph.
IPDPS
Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan
2005 Misc conf
High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters.
HiPC
Sayantan Sur, Uday Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda