U. Fat Chio - RankMe

28 papers C 3Journal 11Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 10-Bit 100 MS/s V ICICDT Pradyumna Vellanki, Yen-Jung Lin, U. Fat Chio, Chua-Chin Wang
2023	J	`jnl`	A random shifting data weighted averaging algorithm for Nyquist-rate DAC. IEICE Electron. Express Jun Yuan, Liangbo Wu, U. Fat Chio, Yuxin Wang, Yan Wang
2020	J	`jnl`	2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang
2020	J	`jnl`	A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. IEEE Trans. Circuits Syst. II Express Briefs Wen-Liang Zeng, Edoardo Bonizzoni, Chi-Wa U, Chi-Seng Lam, Sai-Weng Sin, U. Fat Chio, Franco Maloberti, Rui Paulo Martins
2020	J	`jnl`	Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. IEEE Trans. Circuits Syst. Ji-Xuan Li, Sai-Weng Sin, U. Fat Chio, Ya-Jie Wu, Chi-Seng Lam, Rui Paulo Martins
2019	J	`jnl`	A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang
2018	—	`conf`	An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. A-SSCC U. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins
2017	—	`conf`	A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2016	—	`conf`	An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. ESSCIRC Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai-Weng Sin, Rui Paulo Martins
2014	J	`jnl`	Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013	C	`conf`	A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	J	`jnl`	An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2011	—	`conf`	A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	J	`jnl`	A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010	C	`conf`	A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2010	—	`conf`	An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
2010	J	`jnl`	Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	J	`jnl`	A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. Microelectron. J. Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen
2008	C	`conf`	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	—	`conf`	A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	—	`conf`	A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2006	—	`conf`	A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. APCCAS Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio
2005	J	`jnl`	A multiparameter implantable microstimulator SOC. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh
2004	—	`conf`	A C-less ASK demodulator for implantable neural interfacing chips. ISCAS (4) Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao