Tuo Li

22 papers A* 4A 6C 1Misc 2Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2024 A conf
Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions.
DATE
Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran
2024 J jnl
MP-ORAM: A Novel ORAM Design for Multicore Processor Systems.
IEEE Trans. Dependable Secur. Comput.
Sajid Hussain, Hui Guo, Tuo Li, Sri Parameswaran
2022 A* conf
FaSe: fast selective flushing to mitigate contention-based cache timing attacks.
DAC
Tuo Li, Sri Parameswaran
2022 J jnl
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks.
CoRR
Tuo Li, Sri Parameswaran
2022 A* conf
HWST128: complete memory safety accelerator on RISC-V with metadata compression.
DAC
Hsu-Kang Dow, Tuo Li, Sri Parameswaran
2021 J jnl
COPS: A complete oblivious processing system.
Microprocess. Microsystems
Sajid Hussain, Hui Guo, Tuo Li, Hassaan Saadat, Sri Parameswaran
2021 A* conf
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V.
DAC
Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran
2020 Misc conf
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units.
VLSID
Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
2020 J jnl
Hardware Trojan Mitigation in Pipelined MPSoCs.
ACM Trans. Design Autom. Electr. Syst.
Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2020 J jnl
SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation.
CoRR
Tuo Li, Bradley Hopkins, Sri Parameswaran
2017 J jnl
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
IEEE Trans. Computers
Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2016 J jnl
Processor Design for Soft Errors: Challenges and State of the Art.
ACM Comput. Surv.
Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2016 A conf
RECORD: Reducing register traffic for checkpointing in embedded processors.
DATE
Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
2015 C conf
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.
ISCAS
Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
2015 Misc conf
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA.
VLSID
Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran
2015 — conf
Side channel attacks in embedded systems: A tale of hostilities and deterrence.
ISQED
Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran
2013 A conf
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
DATE
Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2013 — —
Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.
Tuo Li
2013 A conf
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
ICCAD
Tuo Li, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2013 A* conf
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors.
DAC
Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jörg Henkel, Sri Parameswaran
2012 A conf
Fine-grained hardware/software methodology for process migration in MPSoCs.
ICCAD
Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
2012 A conf
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors.
DATE
Tuo Li, Roshan G. Ragel, Sri Parameswaran