Tuo-Hung Hou

28 papers A* 1A 2C 2Journal 13Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
Interplay Between Charge Defects and Ferroelectric Reliability: From Wake-Up, Imprint, Fatigue to Breakdown.
IRPS
Chen-Yi Cho, Tzu-Yi Chao, Yu-Lin Shih, Tzu-Yao Lin, Tuo-Hung Hou
2025 J jnl
Variation-Aware Demonstration and Optimization of Block Floating Point and Integer Neural Network Acceleration on RRAM Compute in-Memory Hardware.
IEEE Trans. Circuits Syst. Artif. Intell.
Ahmed Shaban, Shreshtha Gothalyan, Manan Suri, Tuo-Hung Hou
2024 — conf
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm
VLSI Technology and Circuits
Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu
2024 A conf
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application.
DATE
Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang
2024 — conf
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs.
VLSI Technology and Circuits
Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu
2024 — conf
Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security.
VLSI Technology and Circuits
Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2024 J jnl
Roadmap to Neuromorphic Computing with Emerging Technologies.
CoRR
Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser
2023 C conf
FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices.
ISCAS
Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang
2023 — conf
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.
VLSI Technology and Circuits
Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2022 — conf
A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer.
VLSI Technology and Circuits
Ming-Chun Hong, Yao-jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, Sk. Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou
2022 — conf
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
VLSI-DAT
Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
Hardware-Robust In-RRAM-Computing for Object Detection.
CoRR
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
Hardware-Robust In-RRAM-Computing for Object Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
Two-dimensional materials for artificial synapses: toward a practical application.
Neuromorph. Comput. Eng.
I-Ting Wang, Chih-Cheng Chang, Yen-Yu Chen, Yi-Shin Su, Tuo-Hung Hou
2021 — conf
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.
A-SSCC
Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
2021 J jnl
Progress and Benchmark of Spiking Neuron Devices and Circuits.
Adv. Intell. Syst.
Fu-Xiang Liang, I-Ting Wang, Tuo-Hung Hou
2020 J jnl
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE Using OxRAM Crossbar.
CoRR
Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
2020 C conf
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar.
ISCAS
Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
2020 — conf
Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering.
DRC
Chih-Pin Lin, Hao-Hua Hsu, Tuo-Hung Hou
2019 A* conf
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.
DAC
Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou
2018 J jnl
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
2018 J jnl
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs
Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou
2018 J jnl
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.
CoRR
Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri
2017 J jnl
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse.
CoRR
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
2016 J jnl
3D resistive RAM cell design for high-density storage class memory - a review.
Sci. China Inf. Sci.
Boris Hudec, Chung-Wei Hsu, I-Ting Wang, Wei-Li Lai, Che-Chia Chang, Taifang Wang, Karol Fröhlich, Chia-Hua Ho, Chen-Hsi Lin, Tuo-Hung Hou
2015 J jnl
Crossbar array of selector-less TaO
Microelectron. Reliab.
Chun-Tse Chou, Boris Hudec, Chung-Wei Hsu, Wei-Li Lai, Chih-Cheng Chang, Tuo-Hung Hou
2015 A conf
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
ICCAD
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2010 — conf
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.
SoCC
Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan