Tung Thanh Hoang

15 papers A* 1A 2C 2Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
LAVP: A Latency-Aware Virtual Network Function Placement Strategy for Service Function Chain in Network Function Virtualization.
IEEE Access
Tung Thanh Hoang, Linh Manh Pham, Hoai Son Nguyen
2022 — conf
Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training.
IRPS
Wen Ma, Tung Thanh Hoang, Brian Hoskins, Matthew W. Daniels, Jabez J. McClelland, Yutong Gao, Gina C. Adam, Martin Lueker-Boden
2020 C conf
An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array.
ISCAS
Won Ho Choi, Pi-Feng Chiu, Wen Ma, Gertjan Hemink, Tung Thanh Hoang, Martin Lueker-Boden, Zvonimir Bandic
2016 A conf
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems.
DATE
Tung Thanh Hoang, Amirali Shambayati, Andrew A. Chien
2015 J jnl
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture.
SIGARCH Comput. Archit. News
Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati
2015 — conf
Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators.
ASAP
Tung Thanh Hoang, Amirali Shambayati, Henry Hoffmann, Andrew A. Chien
2015 A* conf
Fast support for unstructured data processing: the unified automata processor.
MICRO
Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien
2014 — conf
Performance and energy limits of a processor-integrated FFT accelerator.
HPEC
Tung Thanh Hoang, Amirali Shambayati, Calvin Deutschbein, Henry Hoffmann, Andrew A. Chien
2012 — conf
Data-Width-Driven Power Gating of Integer Arithmetic Circuits.
ISVLSI
Tung Thanh Hoang, Per Larsson-Edefors
2012 — conf
Viterbi Accelerator for Embedded Processor Datapaths.
ASAP
Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors
2010 J jnl
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2010 C conf
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.
DSD
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors
2010 — conf
Design space exploration for an embedded processor with flexible datapath interconnect.
ASAP
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
2009 A conf
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.
IPDPS
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2009 — conf
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.
SoCC
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors