Tung-Chieh Chen

52 papers A* 7A 10Journal 16Unranked 16
YearRankTypeTitle / Venue / Authors
2026 — ed.
Proceedings of the 2026 International Symposium on Physical Design, ISPD 2026, BonnGermany, March 15-18, 2026
ISPD
Stephan Held, Rickard Ewetz, Tung-Chieh Chen, Gracieli Posser
2026 — conf
Technology-Aware 3D Placement with ILP-Based Region Planning for Soft Modules.
ISPD
Cheng-Xun Song, Minh Anh Phan, Sheng-Tan Huang, Shao-Yun Fang, Tung-Chieh Chen, Kai-Shun Hu, Cindy Chin-Fang Shen
2025 A conf
CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs.
ICCAD
Jingyu Pan, Isaac Jacobson, Zheng Zhao, Tung-Chieh Chen, Guanglei Zhou, Chen-Chia Chang, Vineet Rashingkar, Yiran Chen
2025 J jnl
CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs.
CoRR
Jingyu Pan, Isaac Jacobson, Zheng Zhao, Tung-Chieh Chen, Guanglei Zhou, Chen-Chia Chang, Vineet Rashingkar, Yiran Chen
2025 A* conf
Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging.
DAC
Min-Hung Chen, Cheng-Yen Li, Chuan-Chi Su, Yao-Wen Chang, Tung-Chieh Chen
2024 — conf
Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques.
APCCAS
Chen-Ho Chen, Chien-Nan Jimmy Liu, Wei-Ting Tu, Tung-Chieh Chen, Iris Hui-Ru Jiang
2024 — conf
Introduction to the Panel on EDA Challenges at Advanced Technology Nodes.
ISPD
Tung-Chieh Chen
2024 A conf
Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules.
ICCAD
Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang
2022 J jnl
Flexible Multiple-Objective Reinforcement Learning for Chip Placement.
CoRR
Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2022 A* conf
Flexible chip placement via reinforcement learning: late breaking results.
DAC
Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2021 A* conf
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units.
DAC
Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen
2020 — conf
Automatic Floorplanning for AI SoCs.
VLSI-DAT
Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen
2019 — conf
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs.
ASP-DAC
Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo
2018 — conf
FastPass: Fast timing path search for generalized timing exception handling.
ASP-DAC
Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen
2018 J jnl
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany
2017 A conf
A novel damped-wave framework for macro placement.
ICCAD
Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen
2017 A conf
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs.
ICCAD
Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen
2017 A conf
Blockage-aware terminal propagation for placement wirelength minimization.
ICCAD
Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen
2015 J jnl
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin
2015 J jnl
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho
2015 — conf
An approach to anchoring and placing high performance custom digital designs.
ASP-DAC
Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen
2014 J jnl
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu
2014 J jnl
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang
2013 J jnl
1-D Cell Generation With Printability Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin
2013 A* conf
Double patterning lithography-aware analog placement.
DAC
Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang
2013 A conf
Efficient analog layout prototyping by layout reuse with routing preservation.
ICCAD
Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin
2013 — conf
Lithography-aware 1-dimensional cell generation.
ECCTD
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen
2013 A* conf
Routability-driven placement for hierarchical mixed-size circuit designs.
DAC
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang
2012 — conf
Challenges and solutions in modern analog placement.
VLSI-DAT
Tung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng
2012 A conf
Performance-driven analog placement considering monotonic current paths.
ICCAD
Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu
2011 — conf
Automated placement for custom digital designs.
ISPD
Tung-Chieh Chen
2011 A conf
Fast analog layout prototyping for nanometer design migration.
ICCAD
Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen
2009 J jnl
Essential Issues in Analytical Placement Algorithms.
Inf. Media Technol.
Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen
2009 J jnl
Essential Issues in Analytical Placement Algorithms.
IPSJ Trans. Syst. LSI Des. Methodol.
Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen
2008 J jnl
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
2008 A* conf
An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
DAC
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
2008 J jnl
Effective Wire Models for X-Architecture Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
2008 J jnl
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
2008 J jnl
Metal-Density-Driven Placement for CMP Variation and Routability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008 — conf
Metal-density driven placement for cmp variation and routability.
ISPD
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008 J jnl
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2008 — ch.
Packing Floorplan Representations.
Handbook of Algorithms for Physical Design Automation
Tung-Chieh Chen, Yao-Wen Chang
2007 A* conf
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
DAC
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
2007 — ch.
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.
Modern Circuit Placement
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2007 — conf
X-architecture placement based on effective wire models.
ISPD
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
2006 A conf
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.
ICCAD
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2006 J jnl
Modern Floorplanning Based on B
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Yao-Wen Chang
2006 — conf
NTUplace2: a hybrid placer using partitioning and analytical techniques.
ISPD
Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2005 A conf
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.
ICCAD
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
2005 — conf
Modern floorplanning based on fast simulated annealing.
ISPD
Tung-Chieh Chen, Yao-Wen Chang
2005 — conf
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.
ISPD
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
2005 — conf
SoC test scheduling using the B-tree based floorplanning technique.
ASP-DAC
Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang