Tun Li - RankMe

45 papers A 2B 4C 9Misc 2Journal 10Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Adaptive density clustering for data-driven password mangling rule generation. Comput. Secur. Yongtao Luo, Chunye Gong, Jie Liu, Tun Li
2026	J	`jnl`	SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models. CoRR Yuhuan Xia, Tun Li, Hongji Zhou, Xianfa Zhou, Chong Chen, Ruiyu Zhang
2025	—	`conf`	A Parallel Implementation of ChaCha20 on MT-3000 Heterogeneous Multi-zone Processor. ICA3PP (1) Yongtao Luo, Jie Liu, Tun Li, Chunye Gong
2025	J	`jnl`	An efficient heterogeneous parallel password recovery system on MT-3000. J. Supercomput. Yongtao Luo, Jie Liu, Chunye Gong, Tun Li
2025	B	`conf`	COF: Cycle and transmission co-mapping framework for CNN mapping in PIM architecture. ICPP Xianfa Zhou, Tun Li, Yuhuan Xia, Ruiyu Zhang
2025	A	`conf`	IA-Chol: Input-Aware Cholesky Decomposition on CPU and GPU. ICS Jixiao Deng, Qinglin Wang, Lin Chen, Tun Li, Bo Yang, Xinhai Chen, Jie Liu
2025	J	`jnl`	PyABV: a framework for enhancing PyRTL with assertion-based verification. Frontiers Comput. Sci. Yue Cheng, Tun Li, Hongji Zou, WanXia Qu
2024	J	`jnl`	Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu
2023	—	`conf`	ESFO: Equality Saturation for FIRRTL Optimization. ACM Great Lakes Symposium on VLSI Yan Pi, Hongji Zou, Tun Li, WanXia Qu, Hai Wan
2023	C	`conf`	Towards Accelerating Assertion Coverage Using Surrogate Logic Models. ISCAS Tun Li, Mingchuan Shi, Hongji Zou, WanXia Qu
2022	J	`jnl`	Grammar-based fuzz testing for microprocessor RTL design. Integr. Dan Luo, Tun Li, Liqian Chen, Hongji Zou, Mingchuan Shi
2022	A	`conf`	Towards Implementing RTL Microprocessor Agile Design Using Feature Oriented Programming. DATE Hongji Zou, Mingchuan Shi, Tun Li, WanXia Qu
2021	C	`conf`	On Enhancing Application-Ability Training in Discrete Mathematics. FIE Tun Li, Wanwei Liu, Liqian Chen, Xiaoguang Mao
2021	—	`conf`	Rectified Multi-class AdaBoost for Noisy Dataset Based on Weight Adjustment Standard. ASSE Keke Hu, Wanwei Liu, Tun Li
2021	C	`conf`	Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design. ISCAS Tun Li, Hongji Zou, Dan Luo, WanXia Qu
2020	Misc	`conf`	Compiling FL SETTA Wanwei Liu, Liangze Yin, Tun Li
2020	J	`jnl`	Software testing without the oracle correctness assumption. Frontiers Comput. Sci. Tun Li, Wanwei Liu, Xinrui Guo, Ji Wang
2020	J	`jnl`	Towards functional verifying a family of systemC TLMs. Frontiers Comput. Sci. Tun Li, Jun Ye, Qingping Tan
2015	—	`conf`	Equivalence checking of scheduling in high-level synthesis. ISQED Tun Li, Jian Hu, Yang Guo, Sikun Li, Qingping Tan
2013	—	`conf`	Application specified soft error failure rate analysis using sequential equivalence checking techniques. ASP-DAC Tun Li, Dan Zhu, Sikun Li, Yang Guo
2013	J	`jnl`	Bounded Model Checking of ETL Cooperating with Finite and Looping Automata Connectives. J. Appl. Math. Rui Wang, Wanwei Liu, Tun Li, Xiaoguang Mao, Ji Wang
2013	—	`conf`	Efficient translation validation of high-level synthesis. ISQED Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma
2013	B	`conf`	Introduction to programming: science or art? ITiCSE Tun Li, Wanwei Liu, Xiaoguang Mao, Huiping Zhou
2013	—	`conf`	Translation validation of scheduling in high level synthesis. ACM Great Lakes Symposium on VLSI Tun Li, Yang Guo, Wanwei Liu, Mingsheng Tang
2011	—	`conf`	FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming. IPDPS Workshops Jun Ye, Qingping Tan, Tun Li, GuoRong Cao
2011	—	`conf`	Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approach. ISQED Jun Ye, Qingping Tan, Tun Li
2010	C	`conf`	Feature-Oriented Refactoring Proposal for Transaction Level Models in SoCLib. FDL Jun Ye, Qingping Tan, Tun Li, Bin Wu, Yuanru Meng
2009	C	`conf`	The application of Aspectual Feature Module in the development and verification of SystemC models. FDL Jun Ye, Tun Li, Qingping Tan
2008	—	`conf`	2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. ISQED Dan Zhu, Tun Li, Yang Guo, Sikun Li
2008	—	`conf`	Explicit Model Checking Based on Integer Pointer and Fibonacci Hash. ICYCS WanXia Qu, Tun Li, Yang Guo, Xiaodong Yang
2007	C	`conf`	A Novel Collaborative Verification Environment for SoC Co-Verification. CSCWD Tun Li, Sikun Li, Jinshan Yu, Yang Guo
2007	—	`conf`	Coverage Driven Test Generation Framework for RTL Functional Verification. CAD/Graphics Yang Guo, WanXia Qu, Tun Li, Sikun Li
2007	—	`conf`	Experiences Teaching Functional Verification Techniques with Practical Designs. MSE Tun Li, Yang Guo, Sikun Li, Wei Dong, Rangyu Deng
2006	C	`conf`	Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation. EUC Jinshan Yu, Tun Li, Yang Guo, Qingping Tan
2005	—	`conf`	Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. MICAI Tun Li, Yang Guo, Sikun Li, Dan Zhu
2005	—	`conf`	Automatic functional test program generation for microprocessor verification. ASP-DAC Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li
2005	C	`conf`	Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. DSD Tun Li, Yang Guo, Gongjie Liu, Sikun Li
2005	C	`conf`	MA2TG: A Functional Test Program Generator for Microprocessor Verification. DSD Tun Li, Dan Zhu, Yang Guo, Gongjie Liu, Sikun Li
2005	B	`conf`	Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. ATVA Tun Li, Yang Guo, Sikun Li, Gongjie Liu
2004	—	`conf`	Assertion-based automated functional vectors generation using constraint logic programming. ACM Great Lakes Symposium on VLSI Tun Li, Yang Guo, Sikun Li
2004	J	`jnl`	Automatic Circuit Extractor for HDL Description Using Program Slicing. J. Comput. Sci. Technol. Tun Li, Yang Guo, Sikun Li
2004	B	`conf`	CLP Based Static Property Checking. ATVA Tun Li, Yang Guo, Sikun Li
2004	Misc	`conf`	Design and Implementation of a Parallel Verilog Simulator: PVSim. VLSI Design Tun Li, Yang Guo, Sikun Li
2004	—	`conf`	Parallel verilog simulation: architecture and circuit partition. ASP-DAC Tun Li, Yang Guo, Sikun Li, Fujiang Ao, Gongjie Li
2003	—	`conf`	An Automatic Circuit Extractor for RTL Verification. Asian Test Symposium Tun Li, Yang Guo, Sikun Li