Tsuyoshi Iwagaki

30 papers A 1B 4C 6Journal 7Unranked 12

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue
2019	—	`conf`	An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. ITC-Asia Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue
2019	J	`jnl`	Compact and Accurate Digital Filters Based on Stochastic Computing. IEEE Trans. Emerg. Top. Comput. Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue
2019	—	`conf`	State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines. DFT Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue
2017	—	`conf`	State assignment for fault tolerant stochastic computing with linear finite state machines. ITC-Asia Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue
2015	B	`conf`	A practical approach for logic simplification based on fault acceptability for error tolerant application. ETS Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue
2015	B	`conf`	Designing area-efficient controllers for multi-cycle transient fault tolerant systems. ETS Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue
2015	C	`conf`	Logic simplification by minterm complement for error tolerant application. ICCD Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue
2014	C	`conf`	Compact and accurate stochastic circuits with shared random number sources. ICCD Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue
2014	—	`conf`	Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. DFT Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue
2013	—	`conf`	A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. Asian Test Symposium Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue
2012	C	`conf`	Modeling economics of LSI design and manufacturing for test design selection. ICCD Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue
2012	—	`conf`	Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. APCCAS Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue
2011	J	`jnl`	Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2011	J	`jnl`	Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
2011	C	`conf`	Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. DDECS Tsuyoshi Iwagaki, Kewal K. Saluja
2010	—	`conf`	A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties. DELTA Tsuyoshi Iwagaki, Mineo Kaneko
2009	—	`conf`	On the derivation of a minimum test set in high quality transition testing. LATW Tsuyoshi Iwagaki, Mineo Kaneko
2009	J	`jnl`	Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2009	—	`conf`	Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008	J	`jnl`	Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008	C	`conf`	Safe clocking register assignment in datapath synthesis. ICCD Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2007	A	`conf`	Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
2006	J	`jnl`	A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Trans. Inf. Syst. Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara
2006	C	`conf`	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006	—	`conf`	Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2005	B	`conf`	Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. ETS Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2005	—	`conf`	Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki
2004	B	`conf`	A design methodology to realize delay testable controllers using state transition information. ETS Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2003	—	`conf`	Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara