Tsutomu Yoshimura

27 papers C 5Journal 11Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	Analysis of the Electromagnetic Coupling of Two Phase-Locked Loops. ISCAS Ryuji Komabayashi, Tsutomu Yoshimura
2022	J	`jnl`	Self-Coupling and Mutual Pulling in Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura
2021	—	`conf`	Mitigation of Mutual Pulling in Two Phase-locked Loops. NEWCAS Tsutomu Yoshimura
2021	J	`jnl`	Study of Injection Pulling of Oscillators in Phase-Locked Loops. IEEE Trans. Very Large Scale Integr. Syst. Tsutomu Yoshimura
2019	J	`jnl`	Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Takao Kihara, Tomoya Takahashi, Tsutomu Yoshimura
2019	C	`conf`	Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOs. ISCAS Takao Kihara, Keisuke Miyakoshi, Tsutomu Yoshimura
2018	C	`conf`	A Design of Engineering PBL on Embedded System for Novice Freshmen Students. TENCON Hiroyuki Kobayashi, Kazuo Kumamoto, Tsutomu Yoshimura, Toshio Haga, Muneyoshi Iyota, Makoto Katoh
2018	—	`conf`	A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers. APCCAS Yuma Isobe, Takao Kihara, Tsutomu Yoshimura
2018	—	`conf`	A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder. APCCAS Fukuyama Tokuya, Takao Kihara, Tsunehiro Yoshio, Tsutomu Yoshimura
2018	—	`conf`	Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. APCCAS Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura
2017	C	`conf`	Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers. ISCAS Takao Kihara, Hiroyuki Yano, Tsutomu Yoshimura
2017	—	`conf`	Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers. ICECS Tomoya Takahashi, Takao Kihara, Tsutomu Yoshimura
2017	—	`conf`	Spur reduction by self-injection loop in a fractional-N PLL. ICECS Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura
2016	—	`conf`	A 2.6GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection. NEWCAS Naohiro Fujii, Shuei Morishita, Takao Kihara, Tsutomu Yoshimura
2016	—	`conf`	A study on fast motion estimation algorithm. GCCE Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
2016	—	`conf`	Analysis and design of differential LNAs with on-chip transformers in 65-nm CMOS technology. NEWCAS Takao Kihara, Shigesato Matsuda, Tsutomu Yoshimura
2015	C	`conf`	Subharmonically injection-locked PLL with variable pulse-width injections. ISCAS Shuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura
2014	—	`conf`	Analysis and modeling of oscillators with interference noise. ICECS Shinji Shimizu, Junki Mizuno, Shuei Morishita, Koichiro Hida, Tsutomu Yoshimura
2014	J	`jnl`	Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2013	J	`jnl`	Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
2012	J	`jnl`	Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2011	J	`jnl`	Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
2006	J	`jnl`	A study of interference in synchronous systems. IEEE Trans. Circuits Syst. I Regul. Pap. Tsutomu Yoshimura, Atsushi Iwata
2004	J	`jnl`	An analysis of interference in synchronous systems. IEICE Electron. Express Tsutomu Yoshimura, Atsushi Iwata
2002	—	`conf`	A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology. CICC Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1996	J	`jnl`	A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi