Tsutomu Yoshihara

43 papers Journal 34Unranked 9

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters. IEICE Trans. Commun. Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
2013	J	`jnl`	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto
2013	J	`jnl`	Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator. IEICE Trans. Electron. Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
2012	—	`conf`	A CMOS voltage reference combining body effect with switched-current technique. ISOCC Ning Ren, Hao Zhang, Tsutomu Yoshihara
2012	—	`conf`	A novel charge recovery logic structure with complementary pass-transistor network. ISOCC Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara
2012	J	`jnl`	An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
2012	—	`conf`	High efficiency multi-channel LED driver based on SIMO switch-mode converter. ISOCC Luchen Yu, Yuan Zhu, Minjie Chen, Tsutomu Yoshihara
2011	—	`conf`	A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic. A-SSCC Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara
2011	—	`conf`	A non-rectifier wireless power transmission system using on-chip inductor. ASICON Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara
2011	—	`conf`	A novel charge sharing charge pump for energy harvesting application. ISOCC Jiemin Zhou, Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara
2011	J	`jnl`	An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory. IEICE Trans. Electron. Mengshu Huang, Leona Okamura, Tsutomu Yoshihara
2011	J	`jnl`	An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic. IEICE Trans. Electron. Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara
2011	—	`conf`	CMOS low-power subthreshold reference voltage utilizing self-biased body effect. ASICON Hao Zhang, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara
2011	—	`conf`	Double charge pump circuit with triple charge sharing clock scheme. ASICON Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara
2011	—	`conf`	Word error control algorithm through multi-reading for NAND Flash memories. ASICON Chong Zhang, Tsutomu Yoshihara
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2005	J	`jnl`	A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara
2004	J	`jnl`	A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE J. Solid State Circuits Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara
2001	J	`jnl`	A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba
2001	J	`jnl`	Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
2000	J	`jnl`	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara
2000	J	`jnl`	A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
2000	J	`jnl`	A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1994	J	`jnl`	An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara
1994	J	`jnl`	An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
1994	J	`jnl`	Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara
1992	J	`jnl`	A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. IEEE J. Solid State Circuits Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara
1992	J	`jnl`	A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. IEEE J. Solid State Circuits Yoshikazu Miyawaki, Takeshi Nakayama, Shin'ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara
1991	J	`jnl`	A 45-ns 64-Mb DRAM with a merged match-line test architecture. IEEE J. Solid State Circuits Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano
1991	J	`jnl`	A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. IEEE J. Solid State Circuits Takeshi Nakayama, Shin'ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki
1990	J	`jnl`	A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. IEEE J. Solid State Circuits Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara
1990	J	`jnl`	A high-speed parallel sensing architecture for multi-megabit flash E IEEE J. Solid State Circuits Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara
1989	J	`jnl`	120-ns 128 K8-bit/64 K16-bit CMOS EEPROMs. IEEE J. Solid State Circuits Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara
1989	J	`jnl`	A 5 V only one-transistor 256 K EEPROM with page-mode erase. IEEE J. Solid State Circuits Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara
1989	J	`jnl`	Analysis of coupling noise between adjacent bit lines in megabit DRAMs. IEEE J. Solid State Circuits Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara
1989	J	`jnl`	Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara
1988	J	`jnl`	A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM. IEEE J. Solid State Circuits Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara