Tsutomu Sasao

251 papers A* 4A 5B 6C 13Journal 83Unranked 136
YearRankTypeTitle / Venue / Authors
2025 — conf
Linear Transformations for Iterative Reduction of Variables.
ISMVL
Tsutomu Sasao
2025 — conf
Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Martin Lukac
2024 — conf
Approximate Synthesis for Classification Functions.
ISMVL
Tsutomu Sasao
2024 J jnl
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2024 J jnl
On Easily Reconstructable Logic Functions.
IEICE Trans. Inf. Syst.
Tsutomu Sasao
2023 — conf
A Logical Method to Predict Outcomes After Coronary Artery Bypass Grafting.
ISMVL
Tsutomu Sasao, Anders Holmgren, Patrik Eklund
2023 — conf
Data Mining Using Multi-Valued Logic Minimization.
ISMVL
Tsutomu Sasao
2023 — conf
Decomposition-Based Representation of Symmetric Multiple-Valued Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2023 — conf
Easily Reconstructable Logic Functions.
ISMVL
Tsutomu Sasao
2023 J jnl
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams.
FLAP
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2023 J jnl
On the distribution of sensitivities of symmetric Boolean functions.
CoRR
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
2022 J jnl
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2022 — conf
A Method To Generate Rules From Examples.
ISMVL
Tsutomu Sasao
2022 — conf
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks.
ISMVL
Tsutomu Sasao
2022 — conf
On Decision Diagrams for Maximally Asymmetric Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2022 — conf
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2021 — conf
A Design Method for Multiclass Classifiers.
ISMVL
Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi
2021 J jnl
Classification Functions for Handwritten Digit Recognition.
IEICE Trans. Inf. Syst.
Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi
2021 — conf
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2021 — conf
Linear Decompositions for Multi-Valued Input Classification Functions.
ISMVL
Tsutomu Sasao, Jon T. Butler
2021 J jnl
Realization of Multi-Terminal Universal Interconnection Networks Using Contact Switches.
IEICE Trans. Inf. Syst.
Tsutomu Sasao, Takashi Matsubara, Katsufumi Tsuji, Yoshiaki Koga
2020 — conf
Handwritten Digit Recognition Based on Classification Functions.
ISMVL
Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi
2020 — conf
On Optimum Linear Decomposition of Symmetric Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2020 — conf
On a Realization of Multi-terminal Universal Interconnection Networks using Contact Switches.
ISMVL
Tsutomu Sasao, Takashi Matsubara, Katsufumi Tsuji, Yoshiaki Koga
2020 — conf
On the Minimization of Variables to Represent Partially Defined Classification Functions.
ISMVL
Tsutomu Sasao
2020 — conf
Properties of Multiple-Valued Partition Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
2019 — conf
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2019 — book
Index Generation Functions
Tsutomu Sasao
2019 — conf
Maximally Asymmetric Multiple-Valued Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2019 — conf
On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions.
ISMVL
Tsutomu Sasao
2019 — conf
Realizing all Index Generation Functions by the Row-Shift Method.
ISMVL
Jon T. Butler, Tsutomu Sasao
2019 — conf
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya.
EUROCAST (1)
Radomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada
2018 C conf
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector.
ISCAS
Hiroki Nakahara, Tsutomu Sasao
2018 J jnl
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen
2018 — conf
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2018 — conf
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2018 J jnl
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions.
FLAP
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2018 — ch.
Decomposition of Index Generation Functions Using a Monte Carlo Method.
Advanced Logic Synthesis
Tsutomu Sasao, Jon T. Butler
2018 — conf
On a Memory-Based Realization of Sparse Multiple-Valued Functions.
ISMVL
Tsutomu Sasao
2017 J jnl
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2017 J jnl
A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs.
IEICE Trans. Inf. Syst.
Tsutomu Sasao
2017 J jnl
A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions.
J. Multiple Valued Log. Soft Comput.
Tsutomu Sasao
2017 — conf
A Random Forest Using a Multi-valued Decision Diagram on an FPGA.
ISMVL
Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
2017 — conf
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2017 A conf
An algorithm to find optimum support-reducing decompositions for index generation functions.
DATE
Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi
2017 — conf
Index Generation Functions: Minimization Methods.
ISMVL
Tsutomu Sasao
2016 — conf
A Realization of Index Generation Functions Using Multiple IGUs.
ISMVL
Tsutomu Sasao
2016 — conf
A memory-based realization of a binarized deep convolutional neural network.
FPT
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
2016 J jnl
A set partition number system.
Australas. J Comb.
Jon T. Butler, Tsutomu Sasao
2016 — conf
An Efficient Heuristic for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2016 — conf
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa
2016 J jnl
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division.
SIGARCH Comput. Archit. News
Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
2016 J jnl
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
2016 J jnl
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
2016 — conf
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM.
ISVLSI
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen
2016 — conf
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults.
ISMVL
Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao
2015 — conf
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank.
ARC
Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao
2015 J jnl
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao
2015 — conf
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method.
ISMVL
Tsutomu Sasao
2015 B conf
A deep convolutional neural network based on nested residue number system.
FPL
Hiroki Nakahara, Tsutomu Sasao
2015 B conf
A soft-error tolerant TCAM using partial don't-care keys.
ETS
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
2015 — conf
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai
2015 — conf
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2015 J jnl
High-Speed Hardware Partition Generation.
ACM Trans. Reconfigurable Technol. Syst.
Jon T. Butler, Tsutomu Sasao
2014 J jnl
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs.
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014 — conf
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions.
ISMVL
Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi
2014 J jnl
A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tsutomu Sasao, Yuta Urano, Yukihiro Iguchi
2014 J jnl
A Packet Classifier Based on Prefetching EVMDD (
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014 — conf
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K).
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2014 — conf
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 — book
Applications of Zero-Suppressed Decision Diagrams
Tsutomu Sasao, Jon T. Butler
2014 J jnl
Approach to design a compact reversible low power binary comparator.
IET Comput. Digit. Tech.
Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar, Tsutomu Sasao
2014 J jnl
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2014 J jnl
Head-Tail Expressions for Interval Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Infall Syafalni, Tsutomu Sasao
2014 — conf
Inadmissible Class of Boolean Functions under Stuck-at Faults.
ISMVL
Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
2014 J jnl
Index Generation Functions: Tutorial.
J. Multiple Valued Log. Soft Comput.
Tsutomu Sasao
2014 J jnl
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 J jnl
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2014 — conf
Soft-error tolerant TCAMs for high-reliability packet classifications.
APCCAS
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
2013 — conf
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 C conf
A TCAM generator for packet classification.
ICCD
Infall Syafalni, Tsutomu Sasao
2013 J jnl
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 B conf
A packet classifier using LUT cascades based on EVMDDS (k).
FPL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 — conf
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions.
ISMVL
Tsutomu Sasao
2013 — conf
An Architecture for IPv6 Lookup Using Parallel Index Generation Units.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2013 — conf
Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers.
ISMVL
Tsutomu Sasao
2013 — conf
Hardware Index to Set Partition Converter.
ARC
Jon T. Butler, Tsutomu Sasao
2013 J jnl
Inadmissible Class of Boolean Functions under Stuck-at Faults.
CoRR
Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
2013 — conf
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2013 J jnl
Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation.
J. Multiple Valued Log. Soft Comput.
Tsutomu Sasao
2013 J jnl
On the Numbers of Products in Prefix SOPs for Interval Functions.
IEICE Trans. Inf. Syst.
Infall Syafalni, Tsutomu Sasao
2012 J jnl
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines.
J. Multiple Valued Log. Soft Comput.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 J jnl
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 — conf
A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification.
ISVLSI
Infall Syafalni, Tsutomu Sasao
2012 — conf
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 J jnl
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.
Microprocess. Microsystems
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 — conf
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2012 — conf
Hardware Index to Permutation Converter.
IPDPS Workshops
Jon T. Butler, Tsutomu Sasao
2012 — conf
Linear decomposition of index generation functions.
ASP-DAC
Tsutomu Sasao
2012 — conf
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 — conf
Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation.
ISMVL
Tsutomu Sasao
2012 — conf
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer.
ICA3PP (1)
Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
2012 J jnl
On a wideband fast fourier transform for a radio telescope.
SIGARCH Comput. Archit. News
Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
2012 A conf
Row-shift decompositions for index generation functions.
DATE
Tsutomu Sasao
2011 — conf
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2011 — conf
A Regular Expression Matching Circuit Based on a Decomposed Automaton.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2011 J jnl
A fast segmentation algorithm for piecewise polynomial numeric function generators.
J. Comput. Appl. Math.
Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao
2011 — conf
Fast Hardware Computation of x Mod z.
IPDPS Workshops
Jon T. Butler, Tsutomu Sasao
2011 — conf
Index Generation Functions: Recent Developments.
ISMVL
Tsutomu Sasao
2011 — conf
Index to Constant Weight Codeword Converter.
ARC
Jon T. Butler, Tsutomu Sasao
2011 — conf
Numeric Function Generators Using Piecewise Arithmetic Expressions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 — conf
A Comparison of Architectures for Various Decision Diagram Machines.
ISMVL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 C conf
A Packet Classifier Using a Parallel Branching Program Machine.
DSD
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 J jnl
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.
IEICE Trans. Inf. Syst.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2010 J jnl
A Quaternary Decision Diagram Machine: Optimization of Its Code.
IEICE Trans. Inf. Syst.
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2010 J jnl
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 C conf
A regular expression matching using non-deterministic finite automaton.
MEMOCODE
Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 — conf
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 — conf
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables.
ISMVL
Tsutomu Sasao
2010 C conf
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions.
DSD
Tsutomu Sasao
2010 J jnl
On the number of segments needed in a piecewise linear approximation.
J. Comput. Appl. Math.
C. L. Frenzen, Tsutomu Sasao, Jon T. Butler
2010 J jnl
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
Inf. Media Technol.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 J jnl
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2009 — conf
A Parallel Branching Program Machine for Emulation of Sequential Circuits.
ARC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009 — conf
A Quaternary Decision Diagram Machine and the Optimization of its Code.
ISMVL
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2009 B conf
A virus scanning engine using a parallel finite-input memory machine and MPUs.
FPL
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009 J jnl
Complexities of Graph-Based Representations for Elementary Functions.
IEEE Trans. Computers
Shinobu Nagayama, Tsutomu Sasao
2009 — conf
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2009 — book
Progress in Applications of Boolean Functions
Tsutomu Sasao, Jon T. Butler
2009 C conf
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.
DSD
Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura
2009 C conf
The Parallel Sieve Method for a Virus Scanning Engine.
DSD
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2008 B conf
Numerical function generators using bilinear interpolation.
FPL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2008 — conf
On the Complexity of Classification Functions.
ISMVL
Tsutomu Sasao
2008 C conf
On the Complexity of Error Detection Functions for Redundant Residue Number Systems.
DSD
Tsutomu Sasao, Yukihiro Iguchi
2008 A conf
On the numbers of variables to represent sparse logic functions.
ICCAD
Tsutomu Sasao
2008 C conf
Programmable Numerical Function Generators for Two-Variable Functions.
DSD
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
2008 — conf
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators.
ISMVL
Shinobu Nagayama, Tsutomu Sasao
2007 A conf
A CAM Emulator Using Look-Up Table Cascades.
IPDPS
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2007 J jnl
A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Debatosh Debnath, Tsutomu Sasao
2007 — conf
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays.
ISMVL
Tsutomu Sasao
2007 C conf
An Implementation of an Address Generator Using Hash Memories.
DSD
Tsutomu Sasao, Munehiro Matsuura
2007 J jnl
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Munehiro Matsuura, Tsutomu Sasao
2007 C conf
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
DSD
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 J jnl
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 J jnl
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions.
J. Multiple Valued Log. Soft Comput.
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2007 J jnl
Design Methods of Radix Converters Using Arithmetic Decompositions.
IEICE Trans. Inf. Syst.
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2007 — conf
Implementations of Reconfigurable Logic Arrays on FPGAs.
FPT
Tsutomu Sasao, Hiroki Nakahara
2007 — conf
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams.
ASP-DAC
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 J jnl
Numerical Function Generators Using LUT Cascades.
IEEE Trans. Computers
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
2007 — conf
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2007 — conf
Representations of Elementary Functions Using Edge-Valued MDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao
2006 J jnl
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA.
IEICE Trans. Inf. Syst.
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
2006 J jnl
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2006 — conf
A Soft Error Tolerant LUT Cascade Emulator.
ATS
Hiroki Nakahara, Tsutomu Sasao
2006 — conf
A fast logic simulator using a look up table cascade emulator.
ASP-DAC
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2006 J jnl
Analysis and synthesis of weighted-sum functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsutomu Sasao
2006 J jnl
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2006 — conf
Design Methods for Multiple-Valued Input Address Generators.
ISMVL
Tsutomu Sasao
2006 J jnl
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Debatosh Debnath, Tsutomu Sasao
2006 — conf
Implementation of LPM Address Generators on FPGAs.
ARC
Hui Qin, Tsutomu Sasao, Jon T. Butler
2006 — conf
Implementation of Multiple-Valued CAM Functions by LUT Cascades.
ISMVL
Tsutomu Sasao, Jon T. Butler
2006 — conf
On Designs of Radix Converters Using Arithmetic Decompositions.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2006 — conf
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.
ASP-DAC
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2006 — conf
Representations of Elementary Functions Using Binary Moment Diagrams.
ISMVL
Tsutomu Sasao, Shinobu Nagayama
2005 J jnl
A Design Algorithm for Sequential Circuits Using LUT Rings.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2005 — conf
An FPGA design of AES encryption circuit with 128-bit keys.
ACM Great Lakes Symposium on VLSI
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
2005 J jnl
Average Path Length of Binary Decision Diagrams.
IEEE Trans. Computers
Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
2005 A* conf
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.
DAC
Tsutomu Sasao, Munehiro Matsuura
2005 J jnl
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Debatosh Debnath, Tsutomu Sasao
2005 J jnl
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler
2005 — conf
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem.
ISMVL
Marek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer
2005 — conf
Hardware to Compute Walsh Coefficients.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao
2005 C conf
On LUT Cascade Realizations of FIR Filters.
DSD
Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki
2005 J jnl
On the optimization of heterogeneous MDDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shinobu Nagayama, Tsutomu Sasao
2005 J jnl
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders.
IEICE Trans. Inf. Syst.
Debatosh Debnath, Tsutomu Sasao
2005 B conf
Programmable Numerical Function Generators: Architectures and Synthesis Method.
FPL
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
2005 — conf
Radix Converters: Complexity and Implementation by LUT Cascades.
ISMVL
Tsutomu Sasao
2004 — conf
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2004 — conf
A fast method to derive minimum SOPs for decomposable functions.
ASP-DAC
Tsutomu Sasao, Jon T. Butler
2004 A* conf
A method to decompose multiple-output logic functions.
DAC
Tsutomu Sasao, Munehiro Matsuura
2004 — conf
Efficient computation of canonical form for Boolean matching in large libraries.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
2004 J jnl
Fault Diagnosis for RAMs Using Walsh Spectrum.
IEICE Trans. Inf. Syst.
Atsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao
2004 — conf
Minimization of memory size for heterogeneous MDDs.
ASP-DAC
Shinobu Nagayama, Tsutomu Sasao
2004 — conf
On the Minimization of Average Path Lengths for Heterogeneous MDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao
2003 — conf
Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions.
ISMVL
Tsutomu Sasao
2003 J jnl
Compact Representations of Logic Functions Using Heterogeneous MDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinobu Nagayama, Tsutomu Sasao
2003 — conf
Compact Representations of Logic Functions using Heterogeneous MDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao
2003 — conf
Evaluation of multiple-output logic functions using decision diagrams.
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2003 A* conf
Large-scale SOP minimization using decomposition and functional properties.
DAC
Alan Mishchenko, Tsutomu Sasao
2003 — conf
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2002 J jnl
Bi-Partition of Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi
2002 — conf
Comparison of Decision Diagrams for Multiple-Output Logic Functions.
IWLS
Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
2002 — conf
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.
IWLS
Alan Mishchenko, Tsutomu Sasao
2002 — conf
Representations of Logic Functions Using QRMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
2001 J jnl
A discussion on the history of research in arithmetic andReed-Muller expressions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Radomir S. Stankovic, Tsutomu Sasao
2001 — conf
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic.
ISMVL
Tsutomu Sasao
2001 — conf
On the minimization of SOPs for bi-decomposition functions.
ASP-DAC
Tsutomu Sasao, Jon T. Butler
2001 C conf
Realization of Multiple-Output Functions by Reconfigurable Cascades.
ICCD
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2001 J jnl
Worst and Best Irredundant Sum-of-Products Expressions.
IEEE Trans. Computers
Tsutomu Sasao, Jon T. Butler
2000 — conf
A hardware simulation engine based on decision diagrams (short paper).
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno
2000 — conf
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
2000 — conf
Implementation of Multiple-Output Functions Using PQMDDs.
ISMVL
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2000 — conf
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions.
ISMVL
Tsutomu Sasao
2000 — conf
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams.
ISMVL
Hafiz Md. Hasan Babu, Tsutomu Sasao
2000 A conf
Selection of potentially testable path delay faults for test generation.
ITC
Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
2000 — conf
Three parameters to find functional decompositions.
ASP-DAC
Tsutomu Sasao, Ken-ichi Kurimoto
1999 — conf
Fast Boolean Matching Under Permutation Using Representative.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
1999 — conf
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates.
ISMVL
Debatosh Debnath, Tsutomu Sasao
1999 — conf
Realization of Regular Ternary Logic Functions.
ASP-DAC
Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno
1999 — conf
Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions.
ISMVL
Hafiz Md. Hasan Babu, Tsutomu Sasao
1999 — conf
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions.
ISMVL
Tsutomu Sasao
1998 — conf
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
1998 — conf
Decision Diagrams for Discrete Functions: Classification and Unified Interpretation.
ASP-DAC
Radomir S. Stankovic, Tsutomu Sasao
1998 — conf
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams.
ISMVL
Hafiz Md. Hasan Babu, Tsutomu Sasao
1998 — conf
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.
ISMVL
Jon T. Butler, Tsutomu Sasao
1997 — conf
An optimization of AND-OR-EXOR three-level networks.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
1997 J jnl
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.
IEEE Trans. Computers
Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III
1997 — conf
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.
ISMVL
Tsutomu Sasao, Jon T. Butler
1997 J jnl
Easily Testable Realizations for Generalized Reed-Muller Expressions.
IEEE Trans. Computers
Tsutomu Sasao
1997 — conf
On Decomposition of Kleene TDDs.
Asian Test Symposium
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
1997 — conf
On properties of Kleene TDDs.
ASP-DAC
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
1997 — conf
On the Adders with Minimum Tests.
Asian Test Symposium
Seiji Kajihara, Tsutomu Sasao
1997 — conf
Ternary Decision Diagrams: Survey.
ISMVL
Tsutomu Sasao
1996 — conf
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.
ISMVL
Tsutomu Sasao, Jon T. Butler
1996 J jnl
A simplification method for AND-EXOR expressions for multiple-output functions.
Syst. Comput. Jpn.
Norio Koda, Tsutomu Sasao
1996 — conf
Planarity in ROMDD's of Multiple-Valued Symmetric Functions.
ISMVL
Jon T. Butler, J. L. Nowlin, Tsutomu Sasao
1995 — conf
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions.
ASP-DAC
Debatosh Debnath, Tsutomu Sasao
1995 — conf
Planar Multiple-Valued Decision Diagrams.
ISMVL
Tsutomu Sasao, Jon T. Butler
1994 — conf
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion.
ISMVL
Tsutomu Sasao, Jon T. Butler
1994 — conf
Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams.
ISMVL
Radomir S. Stankovic, Milena Stankovic, Claudio Moraga, Tsutomu Sasao
1994 — conf
Multiple-Valued Combinational Circuits with Feedback.
ISMVL
Jon T. Butler, Tsutomu Sasao
1993 J jnl
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsutomu Sasao
1993 J jnl
Minimization of AND-EXOR Expressions Using Rewrite Rules.
IEEE Trans. Computers
Daniel Brand, Tsutomu Sasao
1992 J jnl
Four-variable AND-EXOR minimum expressions and their properties.
Syst. Comput. Jpn.
Norio Koda, Tsutomu Sasao
1992 — conf
Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams.
ISMVL
Tsutomu Sasao
1991 — conf
A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions.
ISMVL
Tsutomu Sasao
1991 J jnl
Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.
IEEE Trans. Computers
Tsutomu Sasao
1990 — conf
EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.
ISMVL
Tsutomu Sasao
1989 J jnl
On the Optimal Design of Multiple-Valued PLA's.
IEEE Trans. Computers
Tsutomu Sasao
1988 J jnl
Multiple-Valued Logic and Optimization of Programmable Logic Arrays.
Computer
Tsutomu Sasao
1986 A* conf
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.
DAC
Tsutomu Sasao
1985 J jnl
An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs.
IEEE Trans. Computers
Tsutomu Sasao
1984 J jnl
Input Variable Assignment and Output Phase Optimization of PLA's.
IEEE Trans. Computers
Tsutomu Sasao
1981 J jnl
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays.
IEEE Trans. Computers
Tsutomu Sasao
1979 J jnl
Conservative Logic Elements and Their Universality.
IEEE Trans. Computers
Tsutomu Sasao, Kozo Kinoshita
1979 J jnl
On the Number of Fanout-Free Functions and Unate Cascade Functions.
IEEE Trans. Computers
Tsutomu Sasao, Kozo Kinoshita
1978 — conf
An application of multiple-valued logic to a design of programmable logic arrays.
MVL
Tsutomu Sasao
1978 J jnl
Cascade Realization of 3-Input 3-Output Conservative Logic Circuits.
IEEE Trans. Computers
Tsutomu Sasao, Kozo Kinoshita
1978 J jnl
Realization of Minimum Circuits with Two-Input Conservative Logic Elements.
IEEE Trans. Computers
Tsutomu Sasao, Kozo Kinoshita
1976 J jnl
On Magnetic Bubble Logic Circuits.
IEEE Trans. Computers
Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda
1975 J jnl
Easily Testable Sequential Machines with Extra Inputs.
IEEE Trans. Computers
Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita