Tsung-Yi Tsai

17 papers C 1Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.
Circuits Syst. Signal Process.
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee
2021 J jnl
High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors.
Circuits Syst. Signal Process.
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, I-Yu Huang, Yu-Cheng Lin, Tzung-Je Lee, Guan-Ru Chen
2019 J jnl
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations.
Circuits Syst. Signal Process.
Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee
2019 J jnl
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.
IEEE Trans. Very Large Scale Integr. Syst.
Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih
2019 — conf
A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs.
ICICDT
Tsung-Yi Tsai, Ting-Sheng Wang, Yi-Jen Chiu, Chua-Chin Wang
2019 J jnl
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.
IEEE Trans. Circuits Syst. II Express Briefs
Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang
2019 — conf
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems.
ASICON
Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang
2017 J jnl
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.
IEEE Trans. Very Large Scale Integr. Syst.
Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang
2017 — conf
A pipeline ROM-less DDFS using equal-division interpolation.
ISOCC
Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang
2017 J jnl
Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine.
Sensors
Je-Wei Lan, Chia-Hsu Hsieh, I-Yu Huang, Yu-Cheng Lin, Tsung-Yi Tsai, Chua-Chin Wang
2016 — conf
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above.
ICICDT
Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang
2016 C conf
A nano-scale 2×VDD I/O buffer with encoded PV compensation technique.
ISCAS
Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang
2015 J jnl
A 30 V rail-to-rail operational amplifier.
Microelectron. J.
Chua-Chin Wang, Tsung-Yi Tsai, Wen-Je Lu, Chih-Lin Chen, Yi-Lun Wu
2015 — conf
A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology.
ICICDT
Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin
2015 J jnl
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Chua-Chin Wang, Wen-Je Lu, Tsung-Yi Tsai
2013 — conf
An innovative application by incorporating RFID technology with current available glucometer.
iCAST/UMEDIA
Hui-Yuan Liu, Tsung-Yi Tsai, Tai-Kuei Ren
2008 — conf
SIP-Based Cross-Domain Proxy Handoff for Mobile Streaming Services.
ISPAN
Chung-Ming Huang, Chao-Hsien Lee, Jun-Hao Zhuang, Tsung-Yi Tsai, Chi-Chang Liu