Tsung-Te Liu

46 papers A* 2C 6Misc 1Journal 26Unranked 11
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Device Noises Resilient Training and Inference Framework for Smart Sensing on Analog Computing In Memory.
CASES
Xin-You Liu, Chi-Sheng Shih, Tsung-Te Liu, Pei-Kuei Tsung, Chih-Wei Chen, Chieh-Fang Teng
2024 J jnl
An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tsung-Hsi Wu, Chang Shu, Tsung-Te Liu
2024 C conf
Highly Reliable PUF Circuits Using Efficient Post-Processing Stabilization Technique.
ISCAS
Yu-Hsiang Tseng, Shao-Hong Yang, Tsung-Te Liu
2024 A* conf
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips.
DAC
Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li
2023 J jnl
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing.
IEEE J. Solid State Circuits
Chun-Yen Yao, Tsung-Yen Wu, Han-Chung Liang, Yu-Kai Chen, Tsung-Te Liu
2023 J jnl
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shao-Hong Yang, Tsung-Te Liu
2023 J jnl
A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation.
IEEE Trans. Circuits Syst. II Express Briefs
Hua-Chien Chang, Ting Wang, Chi-An Liao, Tsung-Te Liu
2023 J jnl
A Speculative Computation Approach for Energy-Efficient Deep Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui-Xuan Zheng, Ya-Cheng Ko, Tsung-Te Liu
2023 J jnl
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS.
IEEE J. Solid State Circuits
Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu
2023 C conf
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models.
ASRU
Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao
2023 J jnl
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models.
CoRR
Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao
2022 J jnl
A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Long Liou, Jui-Yang Hsu, Chen-Sheng Chen, Alexander H. Liu, Hung-yi Lee, Tsung-Te Liu
2022 J jnl
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Hao Cheng, Meng-Hsueh Lee, Bing-Chen Wu, Tsung-Te Liu
2022 J jnl
A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
You-Cheng Lai, Chun-Yen Yao, Shao-Hong Yang, Ying-Wei Wu, Tsung-Te Liu
2022 J jnl
CIM-Based Smart Pose Detection Sensors.
Sensors
Jyun-Jhe Chou, Ting-Wei Chang, Xin-You Liu, Tsung-Yen Wu, Yu-Kai Chen, Ying-Tuan Hsu, Chih-Wei Chen, Tsung-Te Liu, Chi-Sheng Shih
2022 J jnl
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Ming-Guang Lin, Chi-Tse Huang, Yu-Chuan Chuang, Yi-Ta Chen, Ying-Tuan Hsu, Yu-Kai Chen, Jyun-Jhe Chou, Tsung-Te Liu, Chi-Sheng Shih, An-Yeu Wu
2022 C conf
Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning.
ISCAS
Jung-Chun Liu, Tsung-Te Liu
2021 — conf
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency.
VLSI Circuits
Bing-Chen Wu, Tsung-Te Liu
2021 J jnl
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits.
J. Electron. Test.
Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu
2020 J jnl
A 270-mV 6T SRAM Using Row-Based Dual-Phase V
IEEE Trans. Circuits Syst.
Chen-Hsuan Lu, Ying-Tuan Hsu, Bing-Chen Wu, Tsung-Te Liu
2020 J jnl
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS.
IEEE J. Solid State Circuits
Cheng-Yao Hong, Tsung-Te Liu
2020 J jnl
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm.
IEEE J. Solid State Circuits
Zhen-Yu Liang, Hao-Hsuan Wei, Tsung-Te Liu
2020 J jnl
An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Ling-Yu Yeh, Po-Jen Chen, Chen-Chun Pai, Tsung-Te Liu
2020 — conf
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications.
APCCAS
Chia-Heng Lee, Ying-Tuan Hsu, Tsung-Te Liu, Tzi-Dar Chiueh
2020 — conf
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm.
APCCAS
Ting Wang, Tsung-Te Liu
2019 J jnl
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fu-Yan Xie, Bing-Chen Wu, Tsung-Te Liu
2019 J jnl
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring.
IEEE Trans. Circuits Syst. II Express Briefs
Chia-Yuan Ku, Tsung-Te Liu
2019 J jnl
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shang-Yuan Chang, Bing-Chen Wu, Yi-Long Liou, Rui-Xuan Zheng, Pei-Lin Lee, Tzi-Dar Chiueh, Tsung-Te Liu
2019 C conf
Variation-Resilient Design Techniques for Energy-Constrained Systems.
IOLTS
Bing-Chen Wu, Tsung-Te Liu
2018 J jnl
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory.
J. Low Power Electron.
Bing-Chen Wu, Tsung-Te Liu
2017 — conf
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
VLSI-DAT
Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
2016 J jnl
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu
2015 — conf
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction.
VLSI-DAT
Che-Min Huang, Tsung-Te Liu, Tzi-Dar Chiueh
2014 — conf
Design Technology co-optimization for N10.
CICC
Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen
2013 J jnl
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression.
IEEE J. Solid State Circuits
Tsung-Te Liu, Jan M. Rabaey
2013 A* conf
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
DAC
Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest
2012 — conf
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression.
VLSIC
Tsung-Te Liu, Jan M. Rabaey
2012 — conf
Active RFID: Perpetual wireless communications platform for sensors.
ESSCIRC
Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey
2012 — conf
Statistical Analysis and Optimization of Asynchronous Digital Circuits.
ASYNC
Tsung-Te Liu, Jan M. Rabaey
2011 C conf
A low-leakage parallel CRC generator for ultra-low power applications.
ISCAS
Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey
2011 C conf
Linearity analysis of CMOS passive mixer.
ISCAS
Tsung-Te Liu, Jan M. Rabaey
2010 J jnl
Ultralow-Power Design in Near-Threshold Region.
Proc. IEEE
Dejan Markovic, Cheng C. Wang, Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey
2009 J jnl
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey
2008 — conf
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic.
ASYNC
Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey
2007 J jnl
Exploring Very Low-Energy Logic: A Case Study.
J. Low Power Electron.
Louis P. Alarcón, Tsung-Te Liu, Matthew D. Pierson, Jan M. Rabaey
2004 — conf
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator.
ESSCIRC
Tsung-Te Liu, Chorng-Kuang Wang