Tsung-Hsien Tsai

26 papers A 1B 1C 2Journal 10Unranked 12
YearRankTypeTitle / Venue / Authors
2026 — conf
8.2 A 32Gb/s 12.35Tb/s/mm
ISSCC
Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh
2025 J jnl
Agile combination of advanced booking models for short-term railway arrival forecasting.
Eng. Appl. Artif. Intell.
Tsung-Hsien Tsai
2022 — conf
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.
ISSCC
Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski
2022 J jnl
Discovering a trans-omics biomarker signature that predisposes high risk diabetic patients to diabetic kidney disease.
npj Digit. Medicine
I-Wen Wu, Tsung-Hsien Tsai, Chi-Jen Lo, Yi-Ju Chou, Chi-Hsiao Yeh, Yun-Hsuan Chan, Jun-Hong Chen, Paul Wei-Che Hsu, Heng-Chih Pan, Heng-Jung Hsu, Chun-Yu Chen, Chin-Chan Lee, Yu-Chiau Shyu, Chih-Lang Lin, Mei-Ling Cheng, Chi-Chun Lai, Huey-Kang Sytwu, Ting-Fen Tsai
2021 J jnl
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
2021 J jnl
Air-writing recognition using reverse time ordered stroke context.
J. Vis. Commun. Image Represent.
Tsung-Hsien Tsai, Jun-Wei Hsieh, Chuan-Wang Chang, Chin-Rong Lay, Kuo-Chin Fan
2020 — conf
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
VLSI Circuits
Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny
2020 — conf
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.
VLSI Circuits
Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen
2020 J jnl
Self-evolutionary sibling models to forecast railway arrivals using reservation data.
Eng. Appl. Artif. Intell.
Tsung-Hsien Tsai
2018 — conf
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.
VLSI Circuits
Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski
2017 J jnl
A Cooperative Multihop Transmission Scheme for Two-Way Amplify-and-Forward Relay Networks.
IEEE Trans. Veh. Technol.
Chin-Liang Wang, Ting-Nan Cho, Tsung-Hsien Tsai, Min-Chau Jan
2017 B conf
Air-writing recognition using reverse time ordered stroke context.
ICIP
Tsung-Hsien Tsai, Jun-Wei Hsieh
2016 — conf
A 0.034mm
VLSI Circuits
Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
2016 J jnl
Comparison of Several Confidence Intervals for Median Residual Lifetime with Left-truncated and Right-censored Data.
Commun. Stat. Simul. Comput.
Yunchan Chi, Tsung-Hsien Tsai, Yi-Hsuan Tu, Wen-Yan Tsai
2016 — conf
Dynamic flow aggregation in SDNs for application-aware routing.
CSNDSP
Tsung-Hsien Tsai, Kuochen Wang, Tzu-Yu Chao
2015 — conf
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.
ISSCC
Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski
2015 C conf
Real-time vehicle color identification using symmetrical SURFs and chromatic strength.
ISCAS
Li-Chih Chen, Jun-Wei Hsieh, Hui-Fen Chiang, Tsung-Hsien Tsai
2013 — conf
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
CICC
Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan
2013 — conf
A new sky recognition with using location of sky subimage.
ICIA
Yu-Kumg Chen, Tsung-Hsien Tsai
2013 — conf
Sky recognitions for driving-view images.
ICVES
Yu-Kumg Chen, Tsung-Hsien Tsai
2010 J jnl
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight.
IEEE Trans. Circuits Syst. Video Technol.
Nelson Yen-Chung Chang, Tsung-Hsien Tsai, Po-Hsiung Hsu, Yi-Chun Chen, Tian-Sheuan Chang
2009 J jnl
A temporal case retrieval model to predict railway passenger arrivals.
Expert Syst. Appl.
Tsung-Hsien Tsai
2009 J jnl
Neural network based temporal feature models for short-term railway passenger demand forecasting.
Expert Syst. Appl.
Tsung-Hsien Tsai, Chi-Kang Lee, Chien-Hung Wei
2008 — conf
Case Based Models to Predict Final Sales: A Test of Railway Passenger Arrivals.
DMIN
Tsung-Hsien Tsai
2008 C conf
Data reuse analysis of local stereo matching.
ISCAS
Tsung-Hsien Tsai, Nelson Yen-Chung Chang, Tian-Sheuan Chang
2007 A conf
Real-Time DSP Implementation on Local Stereo Matching.
ICME
Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang