Tsung-Hsien Lin

68 papers A 2C 4Journal 28Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Time-Domain Current-Mode Buck Converter With a PI Compensator Incorporating an Infinite Phase Shift Delay Line. IEEE J. Solid State Circuits Mao-Ling Chiu, I-Fang Lo, Tsung-Hsien Lin
2024	J	`jnl`	An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration. IEEE J. Solid State Circuits Chun-Yu Lin, Wei-Han Chen, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
2023	J	`jnl`	A 0.6-V 12-bit Set-and-Down SAR ADC With a DAC-Based Bypass Window Switching Method. IEEE Trans. Circuits Syst. II Express Briefs Wei-En Lee, Tsung-Hsien Lin
2022	J	`jnl`	A Temperature-Compensated Crystal Oscillator With Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy From -30°C to 90°C. IEEE Trans. Circuits Syst. II Express Briefs Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin
2021	—	`conf`	29.5 A 0.008mm ISSCC Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
2021	—	`conf`	A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration. A-SSCC Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin
2021	J	`jnl`	Intelligent Wireless EEG Measurement System With Electrical and Optogenetic Stimulation for Epileptic Seizure Detection and Suppression. IEEE Access Wei-En Lee, Chieh Tsou, Zhan-Xian Liao, Po-Yen Lu, Tsung-Hsien Lin, Shuenn-Yuh Lee, Chou-Ching K. Lin, Gia-Shing Shieh
2020	—	`conf`	A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique. VLSI-DAT Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, Tsung-Hsien Lin
2020	J	`jnl`	Design of a 0.6-V, 429-MHz FSK Transceiver Using Q-Enhanced and Direct Power Transfer Techniques in 90-nm CMOS. IEEE J. Solid State Circuits Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin
2019	—	`conf`	A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS. A-SSCC Chun-Yu Lin, Yu-Ting Hung, Tsung-Hsien Lin
2019	—	`conf`	An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-µm CMOS Process. VLSI-DAT Deng-Kai Lin, Chih-Chan Tu, Shih-Kai Kuo, Tsung-Hsien Lin
2019	C	`conf`	An Area-Efficient VCO-Based Hall Sensor Readout System for Autofocus Applications. ISCAS Pei-Hsuan Huang, Chih-Chan Tu, Tsung-Hsien Lin
2018	J	`jnl`	Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu
2017	J	`jnl`	A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. Chan-Hsiang Weng, Yung-Yu Lin, Tsung-Hsien Lin
2017	—	`conf`	A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. A-SSCC Chun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin
2017	J	`jnl`	A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS. IEEE J. Solid State Circuits Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin
2017	—	`conf`	An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC. A-SSCC Chih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin
2017	—	`conf`	An ultra-low power 169-nA 32.768-kHz fractional-N PLL. A-SSCC Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin
2016	J	`jnl`	A 330-µW 400-MHz BPSK Transmitter in 0.18- µm CMOS for Biomedical Applications. IEEE Trans. Circuits Syst. II Express Briefs Yi-Lin Tsai, Chun-Yu Lin, Bang-Cyuan Wang, Tsung-Hsien Lin
2016	—	`conf`	A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques. A-SSCC Chun-Yu Lin, Tsung-Hsien Lin
2016	—	`conf`	A 40-nV/VHz 0.0145-mm A-SSCC Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin
2016	J	`jnl`	A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer. IEEE J. Solid State Circuits Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Tsung-Hsien Lin
2016	—	`conf`	An area-efficient wideband CMOS hall sensor system for camera autofocus systems. A-SSCC Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin
2015	—	`conf`	5.3 A 2-channel -83.2dB crosstalk 0.061mm ISSCC Yi-Lin Tsai, Feng-Wen Lee, Tzu-Ying Chen, Tsung-Hsien Lin
2015	—	`conf`	A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer. VLSI-DAT Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin
2015	—	`conf`	A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS. A-SSCC Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin
2015	J	`jnl`	A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C IEEE J. Solid State Circuits Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
2015	—	`conf`	EP2: Lost art? Analog tricks and techniques from the masters. ISSCC Tsung-Hsien Lin, Carlo Samori, Richard Schreier
2014	—	`conf`	A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation. A-SSCC Chih-Chan Tu, Feng-Wen Lee, Dong-Feng Yeih, Tsung-Hsien Lin
2014	—	`conf`	A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique. VLSIC Yi-Lin Tsai, Jian-You Chen, Bang-Cyuan Wang, Tzu-Yu Yeh, Tsung-Hsien Lin
2014	—	`conf`	A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C. A-SSCC Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
2014	J	`jnl`	A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin
2014	—	`conf`	An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS. VLSIC Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin
2014	—	`conf`	An Energy-Efficient QPSK Demodulation Scheme with Injection-Locking Technique for Green Radio Communication. iThings/GreenCom/CPSCom Fu-Chien Huang, Bang-Cyuan Wang, Yi-Lin Tsai, Tsung-Hsien Lin
2014	—	`conf`	An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS. A-SSCC Chih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin
2014	—	`conf`	Analog front-end amplifier for ECG applications with feed-forward EOS cancellation. VLSI-DAT Chih-Chan Tu, Tsung-Hsien Lin
2014	—	`conf`	LMS-based digital background linearization technique for VCO-based delta-sigma ADC. MWSCAS Fu-Chien Huang, Shou-Chen Hsu, Yi-Lin Tsai, Yung-Yu Lin, Tsung-Hsien Lin
2013	J	`jnl`	A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs). IEEE Trans. Circuits Syst. I Regul. Pap. Yao-Hong Liu, Li-Guang Chen, Chun-Yu Lin, Tsung-Hsien Lin
2013	J	`jnl`	A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection. IEEE Trans. Biomed. Circuits Syst. Yu-Jie Huang, Che-Wei Huang, Tsung-Hsien Lin, Chih-Ting Lin, Li-Guang Chen, Po-Yun Hsiao, Bi-Ru Wu, Hsiao-Ting Hsueh, Bing-Jye Kuo, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Shey-Shi Lu
2013	—	`conf`	A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer. VLSI-DAT Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin
2012	—	`conf`	A sensor-merged oscillator-based readout circuit for pizeo-resistive sensing applications. BioCAS Yi-Lin Tsai, Po-Yun Hsiao, Li-Guang Chen, Che-Wei Huang, Hsiao-Ting Hsueh, Chih-Chan Tu, Chih-Ting Lin, Shey-Shi Lu, Tsung-Hsien Lin
2012	—	`conf`	An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filter. VLSI-DAT Wei-Ning Liu, Tsung-Hsien Lin
2012	J	`jnl`	Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee
2011	J	`jnl`	A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation. IEEE Trans. Circuits Syst. II Express Briefs Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin
2011	—	`conf`	A 15-mW 2.4-GHz IEEE 802.15.4 transmitter with a FIR-embedded phase modulator. A-SSCC Yao-Hong Liu, Hao-Hung Lo, Li-Guang Chen, Tsung-Hsien Lin
2011	—	`conf`	A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter. A-SSCC Yu-Cheng Chang, Wei-Hao Chiu, Chen-Chien Lin, Tsung-Hsien Lin
2011	J	`jnl`	A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. IEEE J. Solid State Circuits Chen-Yen Ho, Wei-Shan Chan, Yung-Yu Lin, Tsung-Hsien Lin
2011	J	`jnl`	A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. IEEE Trans. Very Large Scale Integr. Syst. Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, Yu-Hsiang Huang
2011	—	`conf`	An energy-efficient super-regenerative ASK receiver with a ΔΣ-based pulse-width demodulator. A-SSCC Po-Yun Hsiao, Yao-Hong Liu, Tsung-Hsien Lin
2010	C	`conf`	A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. ISCAS Wei-Hao Chiu, Chien-Yuan Cheng, Tsung-Hsien Lin
2010	J	`jnl`	A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers. IEEE J. Solid State Circuits Yao-Hong Liu, Tsung-Hsien Lin
2010	J	`jnl`	A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. IEEE J. Solid State Circuits Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin
2010	C	`conf`	Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. ISCAS Chen-Yen Ho, Yung-Yu Lin, Tsung-Hsien Lin
2009	J	`jnl`	A Wideband PLL-Based G/FSK Transmitter in 0.18 µm CMOS. IEEE J. Solid State Circuits Yao-Hong Liu, Tsung-Hsien Lin
2009	J	`jnl`	Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Tsung-Hsien Lin, Ching-Lung Ti, Yao-Hong Liu
2008	C	`conf`	A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. ISCAS Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin
2008	—	`conf`	A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications. CICC Yao-Hong Liu, Tsung-Hsien Lin
2007	J	`jnl`	A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Tsung-Hsien Lin, Chin-Kung Wu, Ming-Chung Tsai
2007	—	`conf`	A Single-Chip Bluetooth EDR Device in 0.13μm CMOS. ISSCC Bojko Marholev, Michael Pan, Ed Chien, L. Zhang, Rozi Roufoogaran, Steve Wu, Iqbal Bhatti, Tsung-Hsien Lin, Michael S. Kappes, Shahla Khorram, Seema Butala Anand, Alireza Zolfaghari, Jesse Castaneda, C. M. Chien, Brima Ibrahim, Henrik Jensen, H. Kim, Paul Lettieri, Siukai Mak, Jack Lin, Y. C. Wong, R. Lee, M. Syed, Maryam Rofougaran, Ahmadreza Rofougaran
2007	J	`jnl`	An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL. IEEE J. Solid State Circuits Tsung-Hsien Lin, Yu-Jen Lai
2007	—	`conf`	An energy-efficient 1.5-Mbps wireless FSK transmitter with A ∑Δ-modulated phase rotator. ESSCIRC Yao-Hong Liu, Tsung-Hsien Lin
2006	—	`conf`	Low-Power Radio Design for Wireless Smart Sensor Networks. IIH-MSP Wai-Chi Fang, Tsung-Hsien Lin
2004	J	`jnl`	Integrated low-power communication system design for wireless sensor networks. IEEE Commun. Mag. Tsung-Hsien Lin, William J. Kaiser, Gregory J. Pottie
2003	J	`jnl`	A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard. IEEE J. Solid State Circuits Arya Behzad, Zhong Ming Shi, Seema Butala Anand, Li Lin, Keith A. Carter, Michael S. Kappes, Tsung-Hsien Lin, Thinh Nguyen, Dan Yuan, Stephen Wu, Y. C. Wong, Victor Fong, Ahmadreza Rofougaran
2001	J	`jnl`	A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop. IEEE J. Solid State Circuits Tsung-Hsien Lin, William J. Kaiser
2000	—	`conf`	A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop. CICC Tsung-Hsien Lin, William J. Kaiser
1999	A	`conf`	CMOS front-end LNA-mixer of micropower RF wireless systems. ISLPED Razieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser
1998	A	`conf`	CMOS front end components for micropower RF wireless systems. ISLPED Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser