Tsung-Chu Huang

33 papers A 1C 1Journal 7Unranked 24
YearRankTypeTitle / Venue / Authors
2024 — conf
Flosit: Float/Posit Coarchitecture Exploiting Value Location in Neural Network.
ICCE-Taiwan
Yu-Liang Chen, Ren-Xiang Liu, Tsung-Chu Huang
2024 — conf
SievingNet: Ternary-Coded Binary Based Approximate Sieving for Neural Network.
ICCE-Taiwan
Chia-Yu Chou, Tzu-Yi Hung, Tsung-Chu Huang
2023 — conf
Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution.
ICCE-Taiwan
Che Lin, Heng Hsu, Tsung-Chu Huang
2023 — conf
TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters.
ICCE-Taiwan
Ting-Yu Chen, Zong-Yu Wang, Tsung-Chu Huang
2022 — conf
2DAN-BNN: Two-Dimensional AN-Code Decoders for Binarized Neural Networks.
ICCE-TW
Kuan-Yu Huang, Jettae Schroff, Cheng-Di Tsai, Tsung-Chu Huang
2022 — conf
AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators.
ATS
Wan Ju Huang, Hsiao-Wen Fu, Tsung-Chu Huang
2022 — conf
SPINDLE: Self-Pretrainable In-situ Normalizer for Deep Learning Error Function.
ICCE-TW
Jyun-Xin Ke, Siang-En Ciou, Ting-Yu Chen, Tsung-Chu Huang
2021 — conf
AN-Coded Redundant Residue Number System for Reliable Neural Networks.
ICCE-TW
Hsiao-Wen Fu, Ting-Yu Chen, Cheng-Di Tsai, Meng-Wei Shen, Tsung-Chu Huang
2021 — conf
Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics.
ICCE-TW
Ting-Yu Chen, Cheng-Di Tsai, Hsiao-Wen Fu, Yung-Chun Yang, Tsung-Chu Huang
2021 — conf
SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs.
ICCE-TW
Cho-Sheng Lin, Jing Huang, Po-Sheng Chang, Chun-Yen Tsai, Tsung-Chu Huang
2021 — conf
TAIWAN Online: Test AI with AN Codes Online for Automotive Chips.
ITC-Asia
Cheng-Di Tsai, Hsiao-Wen Fu, Ting-Yu Chen, Tsung-Chu Huang
2021 — conf
TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network.
AICAS
Cheng-Di Tsai, Ting-Yu Chen, Hsiao-Wen Fu, Tsung-Chu Huang
2020 — conf
Approximate Computing for Batch Learning in Neural Network.
ICCE-TW
Liang-Yu Lin, Jerrae Schroff, Chia-Cheng Liang, Tsung-Chu Huang
2020 — conf
Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network.
ICCE-TW
Wen-Chang Yang, Shu-Yun Lin, Tsung-Chu Huang
2020 — conf
Residue Number System Design Automation for Neural Network Acceleration.
ICCE-TW
Liang-Yu Lin, Jerrae Schroff, Tsu-Ping Lin, Tsung-Chu Huang
2019 — conf
Low-Cost and Fast Design of Precise Activation Functions in Neural Network.
ICCE-TW
Tsung-Chu Huang, Chun-Hao Chiang, Mo-Han Lin
2019 — conf
Self-Checking Residue Number System for Low-Power Reliable Neural Network.
ATS
Tsung-Chu Huang
2018 — conf
Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM.
ATS
Tsung-Chu Huang, Jeffae Schroff
2015 J jnl
Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes.
IEEE Commun. Lett.
Tsung-Chu Huang
2011 J jnl
High-yield performance-efficient redundancy analysis for 2D memory.
Sci. China Inf. Sci.
Tsung-Chu Huang
2010 — conf
HYPERA: High-Yield Performance-Efficient Redundancy Analysis.
Asian Test Symposium
Tsung-Chu Huang, Kuei-Yeh Lu, Yen-Chieh Huang
2009 J jnl
Multi-valued equal-weight codes for self-checking and matching.
IEEE Commun. Lett.
Tsung-Chu Huang
2008 J jnl
A Low-Power Dependable Berger Code for Fully Asymmetric Communication.
IEEE Commun. Lett.
Tsung-Chu Huang
2007 C conf
Congruence Synchronous Mirror Delay.
ISCAS
Tsung-Chu Huang, Gau-Bin Chang, Ling Li
2002 J jnl
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.
J. Electron. Test.
Kuen-Jong Lee, Tsung-Chu Huang
2001 — conf
A Low-Power LFSR Architecture.
Asian Test Symposium
Tsung-Chu Huang, Kuen-Jong Lee
2001 A conf
A token scan architecture for low power testing.
ITC
Tsung-Chu Huang, Kuen-Jong Lee
2001 J jnl
Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Chu Huang, Kuen-Jong Lee
2000 — conf
Peak-power reduction for multiple-scan circuits during test application.
Asian Test Symposium
Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
1999 — conf
An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Asian Test Symposium
Tsung-Chu Huang, Kuen-Jong Lee
1999 J jnl
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst.
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
1997 — conf
Built-in current sensor designs based on the bulk-driven technique.
Asian Test Symposium
Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
1996 — conf
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Asian Test Symposium
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai