Tsugumichi Shibata

21 papers B 1C 2Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2021 — conf
An Indoor Positioning with a Neural Network Model of TensorFlow for Machine Learning.
ISPACS
Bojun Zheng, Takefumi Masuda, Tsugumichi Shibata
2020 J jnl
Characterization of Multi-Layer Ceramic Chip Capacitors up to mm-Wave Frequencies for High-Speed Digital Signal Coupling.
IEICE Trans. Electron.
Tsugumichi Shibata, Yoshito Kato
2018 — conf
A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase.
ISPACS
Chunhui Pan, Hao San, Tsugumichi Shibata
2017 — conf
A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode.
MIXDES
Chunhui Pan, Hao San, Tsugumichi Shibata
2016 — conf
A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer.
ISPACS
Chunhui Pan, Hao San, Tsugumichi Shibata
2015 C conf
An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor.
ISCAS
Yutaro Ishigaki, Yoichi Tomioka, Tsugumichi Shibata, Hitoshi Kitazawa
2015 J jnl
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip.
IEICE Trans. Electron.
Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
2014 J jnl
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU.
IEICE Trans. Electron.
Ryota Takasu, Yoichi Tomioka, Yutaro Ishigaki, Ning Li, Tsugumichi Shibata, Mamoru Nakanishi, Hitoshi Kitazawa
2014 J jnl
Foreword.
IEICE Trans. Electron.
Tsugumichi Shibata
2013 J jnl
A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI.
IEICE Electron. Express
Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata
2012 C conf
Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs.
ISCAS
Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
2011 — conf
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.
ISOCC
Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
2011 — conf
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON.
A-SSCC
Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
2011 J jnl
An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System.
IEICE Trans. Electron.
Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata
2011 B conf
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction.
GLOBECOM
Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Akihiko Miyazaki, Masami Urano, Tsugumichi Shibata
2005 J jnl
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation.
IEICE Trans. Electron.
Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi
2005 J jnl
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
2004 J jnl
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.
IEEE J. Solid State Circuits
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
2004 — conf
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop].
ESSCIRC
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
2003 J jnl
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator.
IEEE J. Solid State Circuits
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata
1994 J jnl
A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module.
IEEE J. Solid State Circuits
Tsugumichi Shibata, Shunji Kimura, Hideaki Kimura, Yuhki Imai, Yohtaro Umeda, Yukio Akazawa