Tsu-Wei Tseng

19 papers A 4Misc 2Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2014 — conf
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage.
VLSI-DAT
Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai
2013 — conf
Enabling inter-die co-optimization in 3-D IC with TSVs.
VLSI-DAT
Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai
2012 — conf
3-D centric technology and realization with TSV.
VLSI-DAT
Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou
2012 J jnl
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng
2011 J jnl
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Tsu-Wei Tseng, Jin-Fu Li
2011 J jnl
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng
2011 J jnl
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories.
J. Inf. Sci. Eng.
Tsu-Wei Tseng, Jin-Fu Li
2010 J jnl
A Built-in Method to Repair SoC RAMs in Parallel.
IEEE Des. Test Comput.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou
2010 Misc conf
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
VTS
Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li
2010 J jnl
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li
2010 J jnl
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.
IEEE Trans. Very Large Scale Integr. Syst.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu
2010 J jnl
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou
2008 A conf
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs.
ITC
Tsu-Wei Tseng, Jin-Fu Li
2007 Misc conf
A Built-In Self-Repair Scheme for Multiport RAMs.
VTS
Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen
2007 J jnl
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
CoRR
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
2007 J jnl
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng
2006 A conf
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
ITC
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen
2006 A conf
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.
DATE
Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
2005 A conf
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
DATE
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey