Tso-Bing Juang

27 papers C 2Journal 11Unranked 14
YearRankTypeTitle / Venue / Authors
2024 — conf
Design of Automatic Generators for Fibonacci Q- matrix based Encryption/Decryption Circuits.
ISOCC
Tso-Bing Juang, Huang-Sen Chiu
2023 — conf
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS).
ISOCC
Tso-Bing Juang, Chun-Chi Fan, Guan-Zhong Lin
2019 — conf
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems.
ISOCC
Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin
2018 — conf
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems.
ISOCC
Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin
2017 — conf
Low-area implementations of concurrent error detection logarithmic processors.
ISOCC
Tso-Bing Juang, Ying-Ren Lee
2016 — conf
Low-cost concurrent error detection schemes for logarithmic converters.
ISOCC
Tso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu
2016 — conf
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications.
ISVLSI
Tso-Bing Juang, Ying-Ren Lee
2014 — conf
Fast binary to BCD converters for decimal communications using new recoding circuits.
ISIC
Tso-Bing Juang, Yu-Ming Chiu
2012 — conf
A lower error antilogarithmic converter using novel four-region piecewise-linear approximation.
APCCAS
Chao-Tsung Kuo, Tso-Bing Juang
2012 J jnl
Multifunction RNS Modulo 2
J. Circuits Syst. Comput.
Tso-Bing Juang, Chao-Tsung Kuo, Go-Long Wu, Jian-Hao Huang
2012 — conf
Multifunction RNS modulo (2
APCCAS
Tso-Bing Juang, Jian-Hao Huang
2012 — conf
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders.
ISOCC
Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo
2011 C conf
Area-efficient 3-input decimal adders using simplified carry and sum vectors.
VLSI-SoC
Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo
2010 — conf
Area-efficient parallel-prefix Ling adders.
APCCAS
Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan
2010 J jnl
Improved Area-Efficient Weighted Modulo 2
IEEE Trans. Circuits Syst. II Express Briefs
Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai
2009 J jnl
50 Years of CORDIC: Algorithms, Architectures, and Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
2009 J jnl
A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng
2009 J jnl
Corrections to "VLSI Design of Diminished-One Modulo 2
IEEE Trans. Circuits Syst. II Express Briefs
Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu
2008 C conf
A novel VLSI iterative divider architecture for fast quotient generation.
ISCAS
Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li
2008 J jnl
Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations.
IEEE Trans. Circuits Syst. II Express Briefs
Tso-Bing Juang
2006 — conf
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations.
APCCAS
Tso-Bing Juang
2005 J jnl
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.
IEICE Trans. Inf. Syst.
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan
2005 J jnl
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee
2005 J jnl
Low-error carry-free fixed-width multipliers with low-cost compensation circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Tso-Bing Juang, Shen-Fu Hsiao
2004 J jnl
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations.
IEEE Signal Process. Lett.
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang
2004 J jnl
Para-CORDIC: parallel CORDIC rotation algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai
2002 — conf
Partition methodology for the final adder in a tree-structure parallel multiplier generator.
APCCAS (1)
Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao