Tsin-Yuan Chang

39 papers A* 2A 1C 3Journal 20Unranked 13
YearRankTypeTitle / Venue / Authors
2019 J jnl
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.
IEEE J. Solid State Circuits
Chih-Wen Lu, Pei-Yi Lai Lee, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou, Poki Chen, Tsin-Yuan Chang, Jenny Yi-Chun Liu
2014 J jnl
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Ruei-Yuan Jou, Tsin-Yuan Chang, Chih-Wen Lu
2014 C conf
A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator.
ISCAS
Hsi-En Liu, Shih-Che Hung, Chih-Wen Lu, Tsin-Yuan Chang
2014 J jnl
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu
2012 J jnl
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Tsin-Yuan Chang
2012 J jnl
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan-Ho Chen, Tsin-Yuan Chang
2012 J jnl
An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems.
IEEE J. Solid State Circuits
Song-Nien Tang, Chi-Hsiang Liao, Tsin-Yuan Chang
2012 J jnl
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To
2011 J jnl
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen
2011 J jnl
Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang
2011 J jnl
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li
2010 J jnl
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang
2010 J jnl
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang
2009 J jnl
IEEE Standard 1500 Compatible Delay Test Framework.
IEEE Trans. Very Large Scale Integr. Syst.
Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang
2008 C conf
A current mode adaptive on-time control scheme for fast transient DC-DC converters.
ISCAS
Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang
2008 J jnl
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement.
IEEE Trans. Circuits Syst. II Express Briefs
Hung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang
2008 — conf
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES.
ISVLSI
Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang
2006 — conf
A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range.
ATS
Chung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang
2006 C conf
A chaos-based pseudo random number generator using timing-based reseeding method.
ISCAS
Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang
2005 — conf
On-chip accumulated jitter measurement for phase-locked loops.
ASP-DAC
Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang
2004 J jnl
A Built-In Parametric Timing Measurement Unit.
IEEE Des. Test Comput.
Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang
2004 — conf
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.
Asian Test Symposium
Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang
2004 — conf
Timing measurement unit with multi-stage TVC for embedded memories.
ASP-DAC
Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang
2003 — conf
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers.
ISCAS (5)
Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong
2002 — conf
An Access Timing Measurement Unit of Embedded Memory.
Asian Test Symposium
Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang
2002 — conf
An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.
Asian Test Symposium
Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang
2001 A conf
A built-in timing parametric measurement unit.
ITC
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
2001 — conf
A low-cost CMOS time interval measurement core.
ISCAS (4)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
2001 — conf
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.
Asian Test Symposium
Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang
2000 — conf
A realistic fault model for flash memories.
Asian Test Symposium
Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang
2000 — conf
SoC Testing and P1500 Standard.
Asian Test Symposium
Tsin-Yuan Chang, Yervant Zorian
1999 J jnl
A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput.
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
1992 — conf
A design for concurrent error detections in FPLAs.
Great Lakes Symposium on VLSI
Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang, Yu-Shen Lin
1992 J jnl
Two schemes for detecting CMOS analog faults.
IEEE J. Solid State Circuits
Tsin-Yuan Chang, Cheng-Chi Wang, Jain-Bean Hsu
1991 J jnl
Design of fault-diagnosable and repairable folded PLAs for yield enhancement.
IEEE J. Solid State Circuits
Chin-Long Wey, Tsin-Yuan Chang, Jyhyeuan Ding
1990 J jnl
An efficient output phase assignment for PLA minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Long Wey, Tsin-Yuan Chang
1990 A* conf
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.
DAC
Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang
1989 J jnl
Design of fault diagnosable and repairable PLA's.
IEEE J. Solid State Circuits
Tsin-Yuan Chang, Chin-Long Wey
1988 A* conf
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.
DAC
Chin-Long Wey, Tsin-Yuan Chang