Tse-Yu Yeh

17 papers A* 7A 1Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2016 J jnl
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.
IEEE Micro
Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
2014 — conf
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache.
ICS 25th Anniversary
Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
2007 J jnl
Low-Power, High-Performance Architecture of the PWRficient Processor Family.
IEEE Micro
Tse-Yu Yeh
2006 — conf
Low-power, high-performance architecture of the PWRficient processor family.
Hot Chips Symposium
Tse-Yu Yeh
2001 J jnl
Understanding branches and designing branch predictors for high-performance microprocessors.
Proc. IEEE
Marius Evers, Tse-Yu Yeh
1998 — conf
Alternative Implementations of Two-Level Adaptive Branch Prediction.
25 Years ISCA: Retrospectives and Reprints
Tse-Yu Yeh, Yale N. Patt
1998 — conf
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.
25 Years ISCA: Retrospectives and Reprints
Tse-Yu Yeh, Yale N. Patt
1996 J jnl
Branch Classification: New Mechanism for Improving Branch Predictor Performance.
Int. J. Parallel Program.
Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
1994 A* conf
Branch classification: a new mechanism for improving branch predictor performance.
MICRO
Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
1993 A* conf
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History.
ISCA
Tse-Yu Yeh, Yale N. Patt
1993 A* conf
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors.
MICRO
Tse-Yu Yeh, Yale N. Patt
1993 A conf
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.
International Conference on Supercomputing
Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
1993 — —
Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors.
Tse-Yu Yeh
1992 A* conf
A comprehensive instruction fetch mechanism for a processor supporting speculative execution.
MICRO
Tse-Yu Yeh, Yale N. Patt
1992 A* conf
Alternative Implementations of Two-Level Adaptive Branch Prediction.
ISCA
Tse-Yu Yeh, Yale N. Patt
1991 A* conf
Single Instruction Stream Parallelism is Greater Than Two.
ISCA
Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
1991 A* conf
Two-Level Adaptive Training Branch Prediction.
MICRO
Tse-Yu Yeh, Yale N. Patt