Tsai-Ming Hsieh

20 papers A 3C 5Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2016 J jnl
Unified approach for simultaneous functional and timing ECO.
IET Circuits Devices Syst.
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
2015 — conf
A logic difference generator with spare cells consideration for ECO synthesis.
ISQED
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
2012 — conf
Image Retrieval based on color and texture features.
FSKD
Chin-Hung Su, Mohd Helmy Abd Wahab, Tsai-Ming Hsieh
2011 — conf
A new ECO technology for functional changes and removing timing violations.
ISQED
Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh
2011 J jnl
Wire Planning for Electromigration and Interference Avoidance in Analog Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hsin-Hsiung Huang, Jui-Hung Hung, Cheng-Chiang Lin, Tsai-Ming Hsieh
2010 J jnl
Optimal Supply Voltage Assignment under Timing, Power and Area Constraints.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hsi-An Chien, Cheng-Chiang Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh
2010 C conf
Technology remapping for engineering change with wirelength consideration.
ISCAS
Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh
2008 C conf
Timing-driven X-architecture router among rectangular obstacles.
ISCAS
Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh
2008 C conf
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.
ISCAS
Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh
2006 C conf
A congestion-driven buffer planner with space reservation.
ISCAS
Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh
2005 — conf
A new congestion and crosstalk aware router.
ISCAS (6)
Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang
2005 — conf
Floorplanning with clock tree estimation.
ISCAS (6)
Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
2004 A conf
A New Effective Congestion Model in Floorplan Design.
DATE
Yi-Lin Hsieh, Tsai-Ming Hsieh
2002 A conf
A New Formulation for SOC Floorplan Area Minimization Problem.
DATE
Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh
2002 — conf
An efficient hierarchical approach for general floorplan area minimization.
APCCAS (2)
Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh
2002 — conf
Sequence-pair based placement with boundary constraints.
ISCAS (1)
Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh
2002 — conf
Structural Decomposition with Functional Considerations for Low Power.
ISQED
Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh
2001 — conf
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint.
ISCAS (5)
Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh
2000 A conf
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract).
FPGA
Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh
2000 C conf
Minimum crosstalk channel routing with dogleg.
ISCAS
Kuo-Chih Hsu, Yu-Chung Lin, Po-Xun Chiu, Tsai-Ming Hsieh