Trong-Yen Lee

60 papers A 1B 5C 6Misc 4Journal 26Unranked 18
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Design and Application of Municipal Service Platform Based on Cloud-Edge Collaboration for Smart Cities.
Sensors
Jingmin Yang, Trong-Yen Lee, Wen-Ta Lee, Li Xu
2022 J jnl
Construction and Implementation of Wireless Network Online Learning System Based on Edge Computing.
Int. J. Emerg. Technol. Learn.
Jingmin Yang, Trong-Yen Lee, Wen-Ta Lee, Li Xu
2021 J jnl
High Efficiency Disease Detection for Potato Leaf with Convolutional Neural Network.
SN Comput. Sci.
Trong-Yen Lee, I-An Lin, Jui-Yuan Yu, Jing-min Yang, Yu-Chun Chang
2021 J jnl
Next-Generation Electronics and Sensing Technology.
Sensors
Trong-Yen Lee, Yen-Lin Chen, Yu-Cheng Fan
2021 J jnl
Smart Cities in China: A Brief Overview.
IT Prof.
Jingmin Yang, Trong-Yen Lee, Wenjie Zhang
2020 J jnl
Design of a FlexRay/Ethernet Gateway and Security Mechanism for In-Vehicle Networks.
Sensors
Trong-Yen Lee, I-An Lin, Ren-Hong Liao
2019 J jnl
A Comprehensive Teaching Reform Model for a Computer Networks Course Based on Integrated Information Systems.
Int. J. Emerg. Technol. Learn.
Jingmin Yang, Trong-Yen Lee, Baoxing Chen, Wenjie Zhang
2019 — conf
Personalized ACC System for Smart Vehicles.
ICCE-TW
Trong-Yen Lee, Po-Hsuan Hung, Ju-Tse Tsai, I-An Lin
2018 J jnl
A Reliability Scheduling Algorithm for the Static Segment of FlexRay on Vehicle Networks.
Sensors
Trong-Yen Lee, I-An Lin, Junjie Wang, Ju-Tse Tsai
2017 — conf
High performance CAN/FlexRay gateway design for in-vehicle network.
DSC
Trong-Yen Lee, Chia-Wei Kuo, I-An Lin
2016 J jnl
A low-area dynamic reconfigurable MDC FFT processor design.
Microprocess. Microsystems
Trong-Yen Lee, Chi-Han Huang, Wei-Cheng Chen, Min-Jea Liu
2016 J jnl
Adaptive instruction codec architecture design for network-on-chip.
Comput. Electr. Eng.
Trong-Yen Lee, Chi-Han Huang, Min-Jea Liu, Jhen-Syuan Chen
2015 — conf
Power-saving dynamic allocati on strategy for clouding server.
ICCE-TW
Trong-Yen Lee, Kuang-Hua Chang, Chi-Han Huang, Cheng-Hsiu Kang, Min-Jea Liu
2014 A conf
Design of Low-Complexity 4-Path Dynamic Reconfigurable MDC FFT Processor.
ICS
Trong-Yen Lee, Wei-Cheng Chen, Chi-Han Huang
2014 J jnl
Design of Smart Power-Saving Architecture for Network on Chip.
VLSI Design
Trong-Yen Lee, Chi-Han Huang
2014 — conf
Energy-saving LED control module for agent-based Micro-Grid systems.
ICCE-TW
Trong-Yen Lee, Chi-Han Huang, Bo-Hao Wang, Cheng-Hsiu Kang, Jen-Yao Chen, I-Hsin Chou
2013 Misc conf
An Efficient Task Placement Method for Reconfigurable FPGA Systems.
CISIS
Trong-Yen Lee, Nian-You Lin, Wei-Cheng Chen, Haixia Wu
2013 Misc conf
Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology.
CISIS
Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, Haixia Wu
2012 — conf
An Efficient Reconfigurable Architecture Design and Implementation of Image Contrast Enhancement Algorithm.
HPCC-ICESS
Wen-Chieh Chen, Shih-Chia Huang, Trong-Yen Lee
2012 J jnl
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.
Integr.
Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee
2012 — conf
Micro fuel cell power management circuit design for portable devices.
FSKD
Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee
2012 Misc conf
Microcontroller based automatic parking system.
ICMLC
Trong-Yen Lee, Chi-Feng Lee
2011 J jnl
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.
Integr.
Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee
2011 J jnl
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
2011 J jnl
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee
2010 — conf
Antenna Violation Avoidance/Fixing for X-clock routing.
ISQED
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
2010 C conf
Double-via insertion enhanced X-architecture clock routing for reliability.
ISCAS
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
2010 J jnl
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems.
J. Inf. Sci. Eng.
Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai
2009 J jnl
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee
2009 J jnl
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion.
Circuits Syst. Signal Process.
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
2009 J jnl
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology.
J. Circuits Syst. Comput.
Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee
2008 J jnl
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
2008 C conf
Layer assignment considering manufacturability in X-architecture clock tree.
CIT
Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee
2008 — conf
X-clock routing based on pattern matching.
SoCC
Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
2007 — conf
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems.
IMECS
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
2007 — conf
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems.
IIH-MSP
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
2007 J jnl
Zero-Skew Driven Buffered RLC Clock Tree Construction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
2006 C conf
A single chip image sensor embedded smooth spatial filter with A/D conversion.
ISCAS
Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao
2006 C conf
Coupling aware RLC-based clock routings for crosstalk minimization.
ISCAS
Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao
2006 — conf
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.
APCCAS
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
2006 — conf
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.
ICICIC (2)
Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai
2006 — conf
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.
APCCAS
Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee
2006 J jnl
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design.
J. Inf. Sci. Eng.
Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu
2005 — conf
A new CCII-based pipelined analog to digital converter.
ISCAS (6)
Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
2005 — conf
A new low-power turbo decoder using HDA-DHDD stopping iteration.
ISCAS (2)
Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
2005 J jnl
SESAG: an object-oriented application framework for real-time systems.
Softw. Pract. Exp.
Pao-Ann Hsiung, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
2005 — conf
Zero-Skew Driven for RLC Clock Tree Construction in SoC.
ICITA (1)
Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee
2004 J jnl
Embedded software synthesis and prototyping.
IEEE Trans. Consumer Electron.
Trong-Yen Lee, Pao-Ann Hsiung
2004 B conf
RCGES: Retargetable Code Generation for Embedded Systems.
ATVA
Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang
2004 J jnl
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software.
IEEE Trans. Software Eng.
Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
2003 B conf
Quasi-Dynamic Scheduling for the Synthesis of Real-Time Embedded Software with Local and Global Deadlines.
RTCSA
Pao-Ann Hsiung, Cheng-Yi Lin, Trong-Yen Lee
2003 B conf
RESS: Real-Time Embedded Software Synthesis and Prototyping Methodology.
RTCSA
Trong-Yen Lee, Pao-Ann Hsiung, I-Mu Wu, Feng-Shi Su
2003 B conf
Software Platform for Embedded Software Development.
RTCSA
Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
2002 C conf
Formal Synthesis and Code Generation of Real-Time Embedded Software using Time-Extended Quasi-Static Scheduling.
APSEC
Pao-Ann Hsiung, Trong-Yen Lee, Feng-Shi Su
2002 B conf
TCN: Scalable Hierarchical Hypercubes.
ICPADS
Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
2002 — conf
VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems.
Symposium on Object-Oriented Real-Time Distributed Computing
Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen
2001 C conf
Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks.
APSEC
Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen
1999 Misc conf
A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System.
PDPTA
Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
1998 J jnl
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems.
ACM Trans. Design Autom. Electr. Syst.
Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
1997 — conf
Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis.
TOOLS (24)
Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen