Trond Ytterdal

89 papers C 9Journal 23Unranked 57

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage. DCIS Muhammad Umer Khalid, Trond Ytterdal, Snorre Aunet
2025	—	`conf`	DTMOS Schmitt-Trigger Standard Cells based Frequency Divider Operating at 60 mV. PRIME Muhammad Umer Khalid, Trond Ytterdal, Snorre Aunet
2025	J	`jnl`	Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism. Circuits Syst. Signal Process. Linknath Surya Balasubramanian, Elijah Racz, Anoop Gopinath, Maher E. Rizkalla, John J. Lee, Trond Ytterdal, Mukesh Kumar
2025	J	`jnl`	Optimizing Energy Efficiency in Subthreshold RISC-V Cores. CoRR Asbjørn Djupdal, Magnus Själander, Magnus Jahre, Snorre Aunet, Trond Ytterdal
2025	—	`conf`	Robust DTMOS Schmitt-Trigger Circuits in 130 nm SOI CMOS for Sub-100mV Supply Voltage. DCIS Muhammad Umer Khalid, Trond Ytterdal, Snorre Aunet
2024	J	`jnl`	Design and Analysis of the Leapfrog Control-Bounded A/D Converter. IEEE Trans. Very Large Scale Integr. Syst. Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal
2024	—	`conf`	Interfacing GaN HEMTs with Josephson Junctions: A Novel Approach to High-Frequency Electronics. MWSCAS Elijah Racz, Arthur Thomas, Maher E. Rizkalla, Trond Ytterdal, John J. Lee
2023	C	`conf`	A 160-GHz Power Amplifier with 32-dB Gain and 9.8% Peak PAE in 28-nm FD-SOI. ISCAS Shankkar Balasubramanian, Carsten Wulff, Trond Ytterdal
2023	—	`conf`	SRAM Vmin Scaling via Negative Wordline. MWSCAS Anoop Gopinath, Trond Ytterdal, Avinash Yadav, John J. Lee, Maher E. Rizkalla, Mukesh Kumar
2023	—	`conf`	Towards No Penalty Control Hazard Handling. MWSCAS Linknath Surya Balasubramanian, Maher E. Rizkalla, Jaehwan Lee, Trond Ytterdal, Mukesh Kumar
2022	—	`conf`	High-level Comparison of Control-Bounded A/D Converters and Continuous- Time Sigma-Delta Modulators. NorCAS Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal
2021	C	`conf`	GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. ISCAS George Mekhael, Nathaniel Morgan, Mounica Patnala, Trond Ytterdal, Maher E. Rizkalla
2021	—	`conf`	Implementation of High Speed and Low Power Carry Select Adder with BEC. MWSCAS Nikhil Advaith Gudala, Trond Ytterdal, John J. Lee, Maher E. Rizkalla
2021	—	`conf`	Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. NorCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2020	—	`conf`	A Low Power FinFET Charge Pump for Energy Harvesting Applications. MWSCAS Kyle Whittaker, Maher E. Rizkalla, Trond Ytterdal
2020	—	`conf`	A Low-power and Low-noise Multi-purpose Chopper Amplifier with High CMRR and PSRR. EMBC Erwin H. T. Shad, Marta Molinas, Trond Ytterdal
2020	—	`conf`	A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural Amplifier. NorCAS Erwin H. T. Shad, Tania Moeinfard, Marta Molinas, Trond Ytterdal
2020	—	`conf`	A Very Low SEF Neural Amplifier by Utilizing a High Swing Current-Reuse Amplifier. DCIS Kebria Naderi, Erwin H. T. Shad, Marta Molinas, Ali Heidari, Trond Ytterdal
2020	J	`jnl`	An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. IEEE Trans. Circuits Syst. Even Låte, Trond Ytterdal, Snorre Aunet
2020	J	`jnl`	Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. IEEE Trans. Very Large Scale Integr. Syst. Even Låte, Trond Ytterdal, Snorre Aunet
2020	—	`conf`	Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. NorCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2020	C	`conf`	Emerging Josephson Junction/Graphene Device Technologies towards THz Signal Generation. ISCAS Zachary Cochran, Trond Ytterdal, Akul Madan, Maher E. Rizkalla
2020	—	`conf`	Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. NorCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2020	J	`jnl`	Plasmonic FET Terahertz Spectrometer. IEEE Access Xueqing Liu, Trond Ytterdal, Michael S. Shur
2019	—	`conf`	A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration. A-SSCC Harald Garvik, Carsten Wulff, Trond Ytterdal
2019	C	`conf`	A High-Voltage Cascode-Connected Three-Level Pulse-Generator for Bio-Medical Ultrasound Applications. ISCAS Aslak Lykre Holen, Trond Ytterdal
2019	J	`jnl`	An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2019	—	`conf`	Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. NORCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2019	—	`conf`	Modified Current-reuse OTA to Achieve High CMRR by utilizing Cross-coupled Load. PRIME Erwin H. T. Shad, Marta Molinas, Trond Ytterdal
2019	—	`conf`	Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. NORCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2018	J	`jnl`	A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. Integr. Even Låte, Trond Ytterdal, Snorre Aunet
2018	—	`conf`	Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. NORCAS Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet
2018	J	`jnl`	Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing. Microprocess. Microsystems Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet
2017	J	`jnl`	A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound. IEEE Trans. Biomed. Circuits Syst. Rune Kaald, Trym Eggen, Trond Ytterdal
2017	J	`jnl`	A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers. IEEE J. Solid State Circuits Carsten Wulff, Trond Ytterdal
2017	J	`jnl`	A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging. IEEE Trans. Biomed. Circuits Syst. Hourieh Attarzadeh, Ye Xu, Trond Ytterdal
2017	—	`conf`	An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation. CICC Harald Garvik, Carsten Wulff, Trond Ytterdal
2017	J	`jnl`	Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocess. Microsystems Even Låte, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2016	—	`conf`	28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. MIXDES Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2016	J	`jnl`	A 54-µW Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Peng Wang, Trond Ytterdal
2016	—	`conf`	A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOI. ESSCIRC Carsten Wulff, Trond Ytterdal
2016	J	`jnl`	Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array. Microelectron. J. Hourieh Attarzadeh, Sung Kyu Lim, Trond Ytterdal
2016	J	`jnl`	Low noise, -50 dB second harmonic distortion single-ended to differential switched-capacitive variable gain amplifier for ultrasound imaging. IET Circuits Devices Syst. Peng Wang, Trond Ytterdal
2016	J	`jnl`	Low-power low-area beamformer design using switched-current ARAM using external capacitors. Microelectron. J. Surya Sharma, Trond Ytterdal
2016	—	`conf`	Neural network based on parametrically-pumped oscillators. ICECS György Csaba, Trond Ytterdal, Wolfgang Porod
2016	C	`conf`	Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs. ISCAS Harald Garvik, Carsten Wulff, Trond Ytterdal
2016	—	`conf`	Steep slope transistors: Tunnel FETs and beyond. ESSDERC Alan C. Seabaugh, Cristobal Alessandri, Mina Asghari Heidarlou, Hua-Min Li, Leitao Liu, Hao Lu, Sara Fathipour, Paolo Paletti, Pratyush Pandey, Trond Ytterdal
2016	—	`conf`	Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. NORCAS Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet
2015	—	`conf`	4 Sub-/near-threshold flip-flops with application to frequency dividers. ECCTD Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2015	C	`conf`	A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. ISCAS Ye Xu, Pieter Harpe, Trond Ytterdal
2015	—	`conf`	A differential inverter-based switched-capacitor oscillator in 65 nm CMOS technology. ECCTD Peng Wang, György Csaba, Wolfgang Porod, Trond Ytterdal
2015	—	`conf`	An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm. NORCAS Hourieh Attarzadeh, Snorre Aunet, Trond Ytterdal
2015	—	`conf`	Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI. NORCAS Even Låte, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2015	—	`conf`	Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS. ECCTD Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2015	J	`jnl`	In-Probe Ultrasound Beamformer Utilizing Switched-Current Analog RAM. IEEE Trans. Circuits Syst. II Express Briefs Surya Sharma, Trond Ytterdal
2015	—	`conf`	Inverter-based Low-power, low-noise SC-VGA and 8 channel pipelined S/H analog beamformer for ultrasound imaging probes. ECCTD Peng Wang, Trond Ytterdal
2015	C	`conf`	Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study. ISCAS Hourieh Attarzadeh, Sung Kyu Lim, Trond Ytterdal
2015	—	`conf`	Surfing front-end architectures for ultrasound imaging systems. ECCTD Peng Wang, Trond Ytterdal, Thomas M. Halvorsrod
2014	—	`conf`	A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers. ISVLSI Hourieh Attarzadeh, Trond Ytterdal
2014	—	`conf`	Modular layout-friendly cell library design applied for subthreshold CMOS. NORCHIP Jonathan Edvard Bjerkedok, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
2014	—	`conf`	Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. NORCHIP Magne Voernes, Trond Ytterdal, Snorre Aunet
2013	—	`conf`	A 65nm CMOS front-end LNA for medical ultrasound imaging with feedback employing noise and distortion cancellation. ECCTD Jon Håvard Eriksrod, Trond Ytterdal
2013	—	`conf`	A 7-bit 50ms/s single-ended asynchronous SAR ADC in 65nm CMOS. NORCHIP Ye Xu, Trond Ytterdal
2013	—	`conf`	A low noise single-end to differential switched-capacitor VGA for PZT-Xducer ultrasound imaging. ECCTD Peng Wang, Trond Ytterdal, Thomas Halvorsrod
2013	—	`conf`	A low noise single-ended to differential linear charge sampling SC-VGA for second harmonic cardiac ultrasound imaging. ECCTD Peng Wang, Trond Ytterdal, Thomas Halvorsrod
2013	—	`conf`	A low power analog RAM implementation for in-probe beamforming in ultrasound imaging. ECCTD Surya Sharma, Trond Ytterdal
2013	—	`conf`	A low-power, low-noise, and low-cost VGA for second harmonic imaging ultrasound probes. BioCAS Peng Wang, Trond Ytterdal, Thomas Moe Halvorsrod
2013	—	`conf`	Low power OTA-less I-V-converter with single-ended to differential conversion for capacitive sensor interfaces. ECCTD Hourieh Attarzadeh, Trond Ytterdal
2013	—	`conf`	Low power front end electronics for in-probe beamforming in ultrasound imaging. NORCHIP Surya Sharma, Trond Ytterdal
2012	—	`conf`	A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS. NORCHIP Tuan Vu Cao, Snorre Aunet, Trond Ytterdal
2012	J	`jnl`	Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Atila Alvandpour, Patrick Reynaert, Trond Ytterdal
2012	C	`conf`	Low noise front-end amplifier design for medical ultrasound imaging applications. VLSI-SoC Surya Sharma, Trond Ytterdal
2012	—	`conf`	Modeling and design of a dual-residue pipelined ADC in 130nm CMOS. NORCHIP Eirik Steen-Hansen, Trond Ytterdal
2011	—	`conf`	Figure-of-merit optimization of a low noise amplifier in 180 nm CMOS. ECCTD Hans Herman Hansen, Trond Ytterdal
2009	J	`jnl`	Analog Circuit Design in Nanoscale CMOS Technologies. Proc. IEEE Lanny L. Lewyn, Trond Ytterdal, Carsten Wulff, Kenneth W. Martin
2009	J	`jnl`	Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability. IEEE Trans. Instrum. Meas. Tajeshwar Singh, Trond Sæther, Trond Ytterdal
2009	J	`jnl`	Feedback Biasing in Nanoscale CMOS Technologies. IEEE Trans. Circuits Syst. II Express Briefs Tajeshwar Singh, Trond Sæther, Trond Ytterdal
2009	J	`jnl`	Resonators in Open-Loop Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Carsten Wulff, Trond Ytterdal
2007	—	`conf`	Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging. ACM Great Lakes Symposium on VLSI Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal
2006	C	`conf`	Jitter analysis of general charge sampling amplifiers. ISCAS Linga Reddy Cenkeramaddi, Trond Ytterdal
2005	—	`conf`	A 220mW 14b 40MSPS gain calibrated pipelined ADC. ESSCIRC Johnny Bjørnsen, Øystein Moldsvor, Trond Sæther, Trond Ytterdal
2005	—	`conf`	Simplified gate level noise injection models for behavioral noise coupling simulation. ECCTD Jan Lundgren, Trond Ytterdal, Mattias O'Nils
2004	—	`conf`	A single-ended to differential capacitive sensor interface circuit designed in CMOS technology. ISCAS (1) Tajeshwar Singh, Trond Ytterdal
2003	—	`conf`	Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC. ISVLSI Jan Lundgren, Bengt Oelmann, Trond Ytterdal, Patrik Eriksson, Munir Abdalla, Mattias O'Nils
2003	—	`conf`	Behavioral modeling and simulation of high-speed analog-to-digital converters using SystemC. ISCAS (3) Johnny Bjørnsen, Trond Ytterdal
2002	—	`conf`	Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. ISCAS (5) Trond Ytterdal, Snorre Aunet
2001	—	`conf`	A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits. ICECS Snorre Aunet, Yngvar Berg, Trond Ytterdal, Øivind Næss, Trond Sæther
2001	—	`conf`	A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications. CICC Thomas E. Bonnerud, Bjørnar Hernes, Trond Ytterdal
2000	—	`conf`	Transistor Modeling for the VDSM Era. ISQED Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal