Travis N. Blalock

17 papers A* 1A 1C 1Journal 7Unranked 7

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR. CICC Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers
2012	J	`jnl`	Tracking On-Chip Age Using Distributed, Embedded Sensors. IEEE Trans. Very Large Scale Integr. Syst. Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, Travis N. Blalock
2010	J	`jnl`	An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock
2010	A*	`conf`	SRAM-based NBTI/PBTI sensor system design. DAC Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan
2009	A	`conf`	A 2.6 µW sub-threshold mixed-signal ECG SoC. ISLPED Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun
2009	—	`conf`	Mobile health monitoring through biotelemetry. BODYNETS Andrew D. Jurik, Jonathan F. Bolus, Alfred C. Weaver, Benton H. Calhoun, Travis N. Blalock
2009	—	`conf`	Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan
2009	C	`conf`	Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors. ISCAS Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock
2008	J	`jnl`	Experimental System Prototype of a Portable, Low-Cost, C-Scan Ultrasound Imaging Device. IEEE Trans. Biomed. Eng. Michael I. Fuller, Karthik Ranganathan, Shiwei Zhou, Travis N. Blalock, John A. Hossack, William F. Walker
2007	—	`conf`	An automated unique tagging system using CMOS process variation. ACM Great Lakes Symposium on VLSI Brandon L. Dell, Jonathan F. Bolus, Travis N. Blalock
2005	—	`conf`	A three-level toggle-avoid bus signaling scheme. ISCAS (2) Yan Zhang, Travis N. Blalock, Mircea R. Stan
2004	J	`jnl`	An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks. IEEE Trans. Dependable Secur. Comput. Girish B. Ratanpal, Ronald D. Williams, Travis N. Blalock
2003	—	`conf`	40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. ACM Great Lakes Symposium on VLSI Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock
2003	—	`conf`	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit. ACM Great Lakes Symposium on VLSI Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock
2001	J	`jnl`	True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction. IEEE J. Solid State Circuits Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts
1992	J	`jnl`	A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier. IEEE J. Solid State Circuits Travis N. Blalock, Richard C. Jaeger
1991	J	`jnl`	A high-speed clamped bit-line current-mode sense amplifier. IEEE J. Solid State Circuits Travis N. Blalock, Richard C. Jaeger