Toyohiko Yoshida

12 papers A 1C 4Misc 1Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2002 J jnl
Code Efficiency Evaluation for Embedded Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
2001 A conf
Evaluation of processor code efficiency for embedded systems.
ICS
Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
1999 — conf
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores.
CICC
Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida
1998 — conf
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications.
CICC
Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi
1998 J jnl
Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding.
J. VLSI Signal Process.
Edgar Holmann, Toyohiko Yoshida, Akira Yamada, Shin-ichi Uramoto
1997 Misc conf
A dual-issue RISC processor for multimedia signal processing.
ICASSP
Hisakazu Sato, Edgar Holmann, Toyohiko Yoshida, Masahito Matsuo, Toru Kengaku
1996 C conf
Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor.
ICCD
Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu
1994 C conf
A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.
ICCD
Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saito, Jun-ichi Hinata
1991 J jnl
The Gmicro/100 32-bit microprocessor.
IEEE Micro
Toyohiko Yoshida, Toru Shimisu, Shigeo Mizugaki, Jun-ichi Hinata
1990 C conf
A strategy for avoiding pipeline interlock delays in a microprocessor.
ICCD
Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito
1989 C conf
A 32-bit microprocessor with high performance bit-map manipulation instructions.
ICCD
Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito
1988 — conf
A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100.
COMPCON
Tom Shimizu, Toyohiko Yoshida, Yuichi Saito, Masahito Matsuo, Tatsuya Enomoto