Tosiron Adegbija

87 papers A 5B 1C 6Misc 2Journal 47Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design. CoRR Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2026	J	`jnl`	Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study. CoRR Yousuf Choudhary, Tosiron Adegbija
2026	J	`jnl`	Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories. CoRR Yousuf Choudhary, Tosiron Adegbija
2026	J	`jnl`	Surrogates, Spikes, and Sparsity: Performance Analysis and Characterization of SNN Hyperparameters on Hardware. CoRR Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija
2025	A	`conf`	Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture. DATE Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija
2025	J	`jnl`	Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Thapliyal, Jürgen Becker, Garrett S. Rose, Tosiron Adegbija, Selçuk Köse
2025	J	`jnl`	Spiking Neural Network Architecture Search: A Survey. CoRR Kama Svoboda, Tosiron Adegbija
2025	J	`jnl`	System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2024	J	`jnl`	A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. CoRR Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2024	J	`jnl`	ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. CoRR Dhruv Gajaria, Tosiron Adegbija
2024	J	`jnl`	An Open-Source Tool for Generating Domain-Specific Accelerators for Resource-Constrained Computing. J. Open Source Softw. David T. Kerns, Tosiron Adegbija
2024	A	`conf`	Are LLMs Any Good for High-Level Synthesis? ICCAD Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2024	J	`jnl`	Are LLMs Any Good for High-Level Synthesis? CoRR Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2024	—	`conf`	CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing. ASAP Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez
2024	J	`jnl`	CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing. CoRR Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez
2024	J	`jnl`	Deep Inverse Design for High-Level Synthesis. CoRR Ping Chang, Tosiron Adegbija, Yuchao Liao, Claudio Talarico, Ao Li, Janet Roveda
2024	J	`jnl`	Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey. IEEE Access Alaba Yusuf, Tosiron Adegbija, Dhruv Gajaria
2024	J	`jnl`	Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture. CoRR Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija
2024	A	`conf`	Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. DATE Ilkin Aliyev, Tosiron Adegbija
2024	J	`jnl`	Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. CoRR Ilkin Aliyev, Tosiron Adegbija
2024	—	`conf`	Message from the Technical Program Chairs; ISVLSI 2024. ISVLSI Garrett S. Rose, Tosiron Adegbija, Selçuk Köse
2024	C	`conf`	PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine. ISCAS Ilkin Aliyev, Tosiron Adegbija
2024	J	`jnl`	PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine. CoRR Ilkin Aliyev, Tosiron Adegbija
2024	J	`jnl`	SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. CoRR Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
2024	J	`jnl`	STT-RAM-Based Hierarchical in-Memory Computing. IEEE Trans. Parallel Distributed Syst. Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija
2024	J	`jnl`	STT-RAM-based Hierarchical In-Memory Computing. CoRR Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija
2024	—	`conf`	Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. ACM Great Lakes Symposium on VLSI Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon
2024	J	`jnl`	Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. CoRR Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon
2024	—	`conf`	Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview. MCSoC Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija, Jean-Marc Fellous
2024	J	`jnl`	Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview. CoRR Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija, Jean-Marc Fellous
2024	J	`jnl`	System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints. CoRR Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2023	J	`jnl`	Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators. CoRR Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija
2023	J	`jnl`	Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija
2023	—	`conf`	Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. ASP-DAC Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2023	Misc	`conf`	Jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research. ICASSP Tosiron Adegbija
2023	J	`jnl`	jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research. CoRR Tosiron Adegbija
2022	C	`conf`	A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. ICCD Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija
2022	—	`conf`	A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. ISVLSI Kyle Kuan, Tosiron Adegbija
2022	J	`jnl`	A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. Sustain. Comput. Informatics Syst. Yuchao Liao, Tosiron Adegbija, Roman Lysecky
2022	J	`jnl`	Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. Future Gener. Comput. Syst. Dhruv Gajaria, Tosiron Adegbija
2022	J	`jnl`	Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing. J. Signal Process. Syst. Dhruv Gajaria, Tosiron Adegbija
2021	A	`conf`	DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing. ISLPED Ankur Limaye, Tosiron Adegbija
2021	J	`jnl`	Energy characterization of graph workloads. Sustain. Comput. Informatics Syst. Ankur Limaye, Antonino Tumeo, Tosiron Adegbija
2020	C	`conf`	A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. ICCD Kyle Kuan, Tosiron Adegbija
2020	J	`jnl`	A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. CoRR Kyle Kuan, Tosiron Adegbija
2020	J	`jnl`	A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. IEEE Trans. Parallel Distributed Syst. Keeley Criswell, Tosiron Adegbija
2020	J	`jnl`	CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks. IEEE Consumer Electron. Mag. Chenxi Dai, Tosiron Adegbija
2020	J	`jnl`	ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Renato Cordeiro, Dhruv Gajaria, Ankur Limaye, Tosiron Adegbija, Nima Karimian, Fatemeh Tehranipoor
2020	J	`jnl`	Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyle Kuan, Tosiron Adegbija
2020	—	`conf`	Message from the Technical Program Chairs iSES 2020. iSES Yasuhiro Takahashi, Tosiron Adegbija, Linga Reddy Cenkeramaddi
2019	J	`jnl`	A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. CoRR Keeley Criswell, Tosiron Adegbija
2019	—	`conf`	ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. MEMSYS Dhruv Gajaria, Tosiron Adegbija
2019	Misc	`conf`	Bit-Wise and Multi-GPU Implementations of the DNA Recombination Algorithm. HiPC Elnaz Tavakoli Yazdi, Ankur Limaye, Ali Akoglu, Tosiron Adegbija, Adam Buntzman
2019	—	`conf`	Energy and Performance Analysis of STTRAM Caches for Mobile Applications. MCSoC Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	Energy and Performance Analysis of STTRAM Caches for Mobile Applications. CoRR Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. CoRR Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems. ISQED Mohamad Hammam Alsafrjalani, Tosiron Adegbija, Lokesh Ramamoorthi
2019	J	`jnl`	HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. CoRR Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. IEEE Trans. Computers Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. ACM Great Lakes Symposium on VLSI Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	Right-Provisioned IoT Edge Computing: An Overview. ACM Great Lakes Symposium on VLSI Tosiron Adegbija, Roman Lysecky, Vinu Vijay Kumar
2019	—	`conf`	SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. IGSC Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
2018	B	`conf`	A Workload Characterization of the SPEC CPU2017 Benchmark Suite. ISPASS Ankur Limaye, Tosiron Adegbija
2018	—	`conf`	AMELIA: An application of the Internet of Things for aviation safety. CCNC Jeremiah Pate, Tosiron Adegbija
2018	J	`jnl`	HERMIT: A Benchmark Suite for the Internet of Medical Things. IEEE Internet Things J. Ankur Limaye, Tosiron Adegbija
2018	A	`conf`	LARS: Logically adaptable retention time STT-RAM cache for embedded systems. DATE Kyle Kuan, Tosiron Adegbija
2018	J	`jnl`	Microprocessor Optimizations for the Internet of Things: A Survey. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross
2018	J	`jnl`	PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking. IEEE Trans. Very Large Scale Integr. Syst. Tosiron Adegbija, Ann Gordon-Ross
2018	—	`conf`	Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges. ISVLSI Islam Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani
2018	—	`conf`	TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems. ACM Great Lakes Symposium on VLSI Mohamad Hammam Alsafrjalani, Tosiron Adegbija
2017	—	`conf`	A Workload Characterization for the Internet of Medical Things (IoMT). ISVLSI Ankur Limaye, Tosiron Adegbija
2017	—	`conf`	Application-Specific Autonomic Cache Tuning for General Purpose GPUs. ICCAC Sam Gianelli, Edward Richter, Diego Jiménez, Hugo Valdez, Tosiron Adegbija, Ali Akoglu
2017	—	`conf`	Coding for Efficient Caching in Multicore Embedded Systems. ISVLSI Tosiron Adegbija, Ravi Tandon
2017	—	`conf`	Exploiting Configurability as a Defense against Cache Side Channel Attacks. ISVLSI Chenxi Dai, Tosiron Adegbija
2017	—	`conf`	PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems. ISVLSI Sam Gianelli, Tosiron Adegbija
2016	—	`conf`	Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems. ACM Great Lakes Symposium on VLSI Tosiron Adegbija
2016	J	`jnl`	Microprocessor Optimizations for the Internet of Things. CoRR Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross
2016	J	`jnl`	Phase distance mapping: a phase-based cache tuning methodology for embedded systems. CoRR Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir
2016	—	`conf`	Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. ISVLSI Tosiron Adegbija, Ann Gordon-Ross
2016	J	`jnl`	Temperature-aware Dynamic Optimization of Embedded Systems. CoRR Tosiron Adegbija, Ann Gordon-Ross
2015	—	`conf`	Phase-based Cache Locking for Embedded Systems. ACM Great Lakes Symposium on VLSI Tosiron Adegbija, Ann Gordon-Ross
2014	C	`conf`	Analysis of cache tuner architectural layouts for multicore embedded systems. IPCCC Tosiron Adegbija, Ann Gordon-Ross, Marisha Rawlins
2014	—	`conf`	Dynamic Phase-Based Optimization of Embedded Systems. ISVLSI Tosiron Adegbija, Ann Gordon-Ross
2014	J	`jnl`	Phase distance mapping: a phase-based cache tuning methodology for embedded systems. Des. Autom. Embed. Syst. Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir
2014	—	`conf`	Thermal-aware phase-based tuning of embedded systems. ACM Great Lakes Symposium on VLSI Tosiron Adegbija, Ann Gordon-Ross
2013	C	`conf`	Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems. ICCD Tosiron Adegbija, Ann Gordon-Ross
2012	C	`conf`	Dynamic phase-based tuning for embedded systems using phase distance mapping. ICCD Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir